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microconverter ? 12-bit adcs and dacs with embedded high speed 62-kb flash mcu ADUC841/aduc842/aduc843 rev. 0 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features pin compatable ugrade of aduc812/aduc831/aduc832 increased performance single-cycle 20 mips 8052 core high speed 420 ksps 12-bit adc increased memory up to 62 kbytes on-chip flash/ee program memory 4 kbytes on-chip flash/ee data memory in-circuit reprogrammable flash/ee, 100 year retention, 100 kcycle endurance 2304 bytes on-chip data ram smaller package 8 mm 8 mm chip scale package 52-lead pqfppin compatable upgrade analog i/o 8-channel, 420 ksps high accuracy, 12-bit adc on-chip, 15 ppm/ c voltage reference dma controller, high speed adc-to-ram capture two 12-bit voltage output dacs 1 dual output pwm -? dacs on-chip temperature monitor function 8052 based core 8051 compatible instruction set (20 mhz max) high performance single-cycle core 32 khz external crystal, on-chip programmable pll 12 interrupt sources, 2 priority levels dual data pointers, extended 11-bit stack pointer on-chip peripherals time interval counter (tic) uart, i 2 c?, and spi? serial i/o watchdog timer (wdt) power supply monitor (psm) power normal: 4.5 ma @ 3 v (core clk = 2.098 mhz) power-down: 10 a @ 3 v 2 development tools low cost, comprehensive development system incorporating nonintrusive single-pin emulation, ide based assembly and c source debugging applications optical networkinglaser power control base station systems precision instrumentation, smart sensors transient capture systems das and communications systems 1 ADUC841/aduc842 only. 2 aduc842/aduc843 only, ADUC841 driven directly by external crystal. functional block diagram 62 kbytes flash/ee program memory 4 kbytes flash/ee data memory 2304 bytes user ram 3 16 bit timers 1 real time clock 4 parallel ports 20 mips 8052 based mcu with additional peripherals ADUC841/aduc842/aduc843 xtal2 xtal1 temp sensor c ref internal band gap vref adc0 adc1 adc5 adc6 adc7 osc 12-bit dac dac 1 pwm0 t/h mux 12-bit adc hardware calibraton buf dac 1 buf pwm1 12-bit dac 16-bit - ? dac 16-bit pwm 16-bit pwm power supply mon watchdog timer uart, i 2 c, and spi serial i/o mux 16-bit - ? dac 03260-0-001 pll 2 figure 1. general description the ADUC841/aduc 842/aduc843 are complete smart transducer front ends, that integrates a high performance self- calibrating multichannel adc, a dual dac, and an optimized single-cycle 20 mhz 8-bit mcu (8051 instruction set compatible) on a single chip. the ADUC841 and aduc842 are identical with the exception of the clock oscillator circuit; the ADUC841 is clocked directly from an external crystal up to 20 mhz whereas the aduc842 uses a 32 khz crystal with an on-chip pll generating a programmable core clock up to 16.78 mhz. the aduc843 is identical to the aduc842 except that the aduc843 has no analog dac outputs. the microcontroller is an optimized 8052 core offering up to 20 mips peak performance. three different memory options are available offering up to 62 kbytes of nonvolatile flash/ee program memory. four kbytes of nonvolatile flash/ee data memory, 256 bytes ram, and 2 kbytes of extended ram are also integrated on-chip. ( continued on page 15)
ADUC841/aduc842/aduc843 rev. 0 | page 2 of 88 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configurations and functional descriptions ........................ 9 terminology .................................................................................... 11 adc specifications .................................................................... 11 dac specifications..................................................................... 11 typical performance characteristics ........................................... 12 functional description .................................................................. 16 8052 instruction set ................................................................... 16 other single-cycle core features ............................................ 18 memory organization ............................................................... 19 special function registers (sfrs)............................................ 20 accumulator sfr (acc)........................................................... 21 special function register banks .............................................. 22 adc circuit information.......................................................... 23 calibrating the adc .................................................................. 30 nonvolatile flash/ee memory ................................................. 31 using flash/ee data memory .................................................. 34 user interface to on-chip peripherals.................................... 38 on-chip pll............................................................................... 41 pulse-width modulator (pwm).............................................. 42 serial peripheral interface (spi)............................................... 45 i 2 c compatible interface........................................................... 48 dual data pointer....................................................................... 51 power supply monitor ............................................................... 52 watchdog timer......................................................................... 53 time interval counter (tic).................................................... 54 8052 compatible on-chip peripherals................................... 57 timer/counter 0 and 1 operating modes.............................. 62 timer/counter operating modes............................................ 64 uart serial interface................................................................ 65 sbuf ............................................................................................ 65 interrupt system ......................................................................... 70 hardware design considerations ............................................ 72 other hardware considerations.............................................. 76 development tools .................................................................... 77 quickstart development system ............................................. 77 timing specifications , , .................................................................. 78 outline dimensions ....................................................................... 86 ordering guides......................................................................... 87 revision history revision 0: initial version
ADUC841/aduc842/aduc843 rev. 0 | page 3 of 88 specifications 1 table 1. av dd = dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; v ref = 2.5 v internal reference, f core = 16.78 mhz @ 5 v 8.38 mhz @ 3 v; all specifications t a = t min to t max , unless otherwise noted parameter v dd = 5 v v dd = 3 v unit test conditions/comments adc channel specifications dc accurac 2, 3 f sample = 120 khz, see the typical performance characteristics for typical performance at other values of f sample resolution 12 12 bits integral nonlinearity 1 1 lsb max 2.5 v internal reference 0.3 0.3 lsb typ differential nonlinearity +1/0.9 +1/0.9 lsb max 2.5 v internal reference 0.3 0.3 lsb typ integral nonlinearity 4 2 1.5 lsb max 1 v external reference differential nonlinearity 4 +1.5/0.9 +1.5/0.9 lsb max 1 v external reference code distribution 1 1 lsb typ adc input is a dc voltage calibrated endpoint errors 5, 6 offset error 3 2 lsb max offset error match 1 1 lsb typ gain error 3 2 lsb max gain error match 1 1 lsb typ dnamic performance f in = 10 khz sine wave f sample = 120 khz signal-to-noise ratio (snr) 7 71 71 db typ total harmonic distortion (thd) 85 85 db typ peak harmonic or spurious noise 85 85 db typ channel-to-channel crosstalk 8 80 80 db typ analog input input voltage range 0 to v ref 0 to v ref v leakage current 1 1 a max input capacitance 32 32 pf typ temperature sensor 9 voltage output at 25c 700 700 mv typ voltage tc 1.4 1.4 mv/c typ accuracy 1.5 1.5 c typ internal/external 2.5 v v ref dac channel specifications dac load to agnd internal buffer enabled ADUC841/aduc842 only r l = 10 k, c l = 100 pf dc accurac 10 resolution 12 12 bits relative accuracy 3 3 lsb typ differential nonlinearity 11 1 1 lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 50 50 mv max v ref range gain error 1 1 max av dd range 1 1 typ v ref range gain error mismatch 0.5 0.5 typ of full-scale on dac1 analog outputs voltage range0 0 to v ref 0 to v ref v typ dac v ref = 2.5 v voltage range1 0 to v dd 0 to v dd v typ dac v ref = v dd output impedance 0.5 0.5 typ
ADUC841/aduc842/aduc843 rev. 0 | page 4 of 88 parameter v dd = 5 v v dd = 3 v unit test conditions/comments dac ac characteristics voltage output settlin g time 15 15 s typ full-scale settling time to within ? lsb of final value digital-to-analog glitch energy 10 10 nv -sec typ 1 lsb change at major carry dac channel specifications 12, 13 internal buffer disabled ADUC841/aduc842 only dc accuracy 10 resolution 12 12 bits relative accuracy 3 3 lsb typ differential nonlinearity 11 ?1 ?1 lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 5 5 mv max v ref range gain error 0.5 0.5 % typ v ref range gain error mismatch 4 0.5 0.5 % typ % of full-scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ dac v ref = 2.5 v reference input/output reference output 14 output voltage (v ref ) 2.5 2.5 v accuracy 10 10 mv max of v ref measured at the c ref pin t a = 25c power supply rejection 65 67 db typ reference temperature coefficient 15 15 ppm/c typ internal v ref power-on time 2 2 ms typ external reference input 15 voltage range (v ref ) 4 1 1 v min v dd v dd v max input impedance 20 20 k typ input leakage 1 1 a max internal band gap deselected via adccon1.6 power supply monitor (psm) dv dd trip point selection range 2.93 3.08 v min v max two trip points selectable in this range programmed via tpd1?0 in psmcon, 3 v part only dv dd power supply trip point accuracy 2.5 % max watchdog timer (wdt) 4 timeout period 0 2000 0 2000 ms min ms max nine timeout periods selectable in this range flash/ee memory reliability characteristics 16 endurance 17 100,000 100,000 cycles min data retention 18 100 100 years min digital inputs input leakage current (port 0, ea ) 10 10 a max v in = 0 v or v dd 1 1 a typ v in = 0 v or v dd logic 1 input current (all digital inputs), sdata, sclock 10 10 a max v in = v dd 1 1 a typ v in = v dd logic 0 input current (ports 1, 2, 3) sdata, sclock ?75 ?25 a max ?40 ?15 a typ v il = 450 mv logic 1 to logic 0 transition current (ports 2 and 3) ?660 ?250 a max v il = 2 v reset ?400 10 10 105 ?140 10 5 35 a typ a max a min a max v il = 2 v v in = 0 v v in = 5 v, 3 v internal pull down v in = 5 v, 3 v internal pull down
ADUC841/aduc842/aduc843 rev. 0 | page 5 of 88 parameter v dd = 5 v v dd = 3 v unit test conditions/comments logic inputs 4 input voltages all inputs except sclo ck, sdata, reset, and xtal1 vinl, input low voltage vinh, input high voltage sdata vinl, input low voltage vinh, input high voltage 0.8 2.0 0.8 2.0 0.4 2.0 0.8 2.0 v max v min v max v min sclock and reset only 4 (schmitt-triggered inputs) v t+ v t? v t+ ? v t? 1.3 3.0 0.8 1.4 0.3 0.85 0.95 0.25 0.4 1.1 0.3 0.85 v min v max v min v max v min v max crystal oscillator logic inputs, xtal1 only v inl , input low voltage 0.8 0.4 v typ v inh , input high voltage 3.5 2.5 v typ xtal1 input capacitance 18 18 pf typ xtal2 output capacitance 18 18 pf typ mcu clock rate 16.78 20 8.38 8.38 mhz max mhz max aduc842/aduc843 only ADUC841 only digital outputs output high voltage (v oh ) 2.4 v min v dd = 4.5 v to 5.5 v 4 v typ i source = 80 a 2.4 v min v dd = 2.7 v to 3.3 v 2.6 v typ i source = 20 a output low voltage (v ol ) ale, ports 0 and 2 0.4 0.4 v max i sink = 1.6 ma 0.2 0.2 v typ i sink = 1.6 ma port 3 0.4 0.4 v max i sink = 4 ma sclock/sdata 0.4 0.4 v max i sink = 8 ma, i 2 c enabled floating state leakage current 4 10 10 a max 1 1 a typ startup time at any core clk at power-on 500 500 ms typ from idle mode 100 100 s typ from power-down mode wake-up with int0 interrupt 150 400 s typ wake-up with spi/i 2 c interrupt 150 400 s typ wake-up with external reset 150 400 s typ after external reset in no rmal mode 30 30 ms typ after wdt reset in normal mode 3 3 ms typ controlled via wdcon sfr
ADUC841/aduc842/aduc843 rev. 0 | page 6 of 88 parameter v dd = 5 v v dd = 3 v unit test conditions/comments power requirements 19, 20 power supply voltages av dd /dv dd ? agnd 2.7 v min av dd /dv dd = 3 v nom 3.6 v max 4.75 v min av dd /dv dd = 5 v nom 5.25 v max power supply currents normal mode 21 dv dd current 4 10 4.5 ma typ core clk = 2.097 mhz av dd current 1.7 1.7 ma max core clk = 2.097 mhz dv dd current 38 12 ma max core clk = 16.78mhz/8.38 mhz 5 v/3 v 33 10 ma typ core clk = 16.78mhz/8.38 mhz 5 v/3 v av dd current 1.7 1.7 ma max core clk = 16.78mhz/8.38 mhz 5 v/3 v dv dd current 4 power supply currents idle mode 21 45 n/a ma max core clk = 20mhz ADUC841 only dv dd current 4.5 2.2 ma typ core clk = 2.097 mhz av dd current 3 2 a typ core clk = 2.097 mhz dv dd current 4 12 5 ma max core clk = 16.78mhz/8.38 mhz 5 v/3 v 10 3.5 ma typ core clk = 16.78mhz/8.38 mhz 5 v/3 v av dd current 3 2 a typ core clk = 16.78mhz/8.38 mhz 5 v/3 v power supply currents power-down mode 21 core clk = any frequency dv dd current 28 20 18 10 a max a typ oscillator off / timecon.1 = 0 av dd current 2 1 a typ core clk = any frequency ADUC841 only dv dd current 4 3 1 ma max timecon.1 = 1 dv dd current 4 50 40 22 15 a max a typ core clk = any frequency aduc842/aduc843 only oscillator on typical additional power supply currents psm peripheral 15 10 a typ av dd = dv dd adc 4 1.0 2.8 1.0 1.8 ma min ma max mclk divider = 32 mclk divider = 2 dac 150 130 a typ see footnotes on the next page.
ADUC841/aduc842/aduc843 rev. 0 | page 7 of 88 1 temperature range ?40c to +85c. 2 adc linearity is guaranteed during no rmal microconverter core operation. 3 adc lsb size = v ref /2 12 , i.e., for internal v ref = 2.5 v, 1 lsb = 610 v, and for external v ref = 1 v, 1 lsb = 244 v. 4 these numbers are not production tested but are supported by design and/or characterization data on production release. 5 offset and gain error and offset and gain e rror match are measured afte r factory calibration. 6 based on external adc system components, the user may need to execute a system calibration to remove additional external chann el errors to achieve these specifications. 7 snr calculation includes distortion and noise components. 8 channel-to-channel crosstalk is measured on adjacent channels. 9 the temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result. 10 dac linearity is calculated using: reduced code range of 100 to 4095, 0 v to v ref range. reduced code range of 100 to 3945, 0 v to v dd range. dac output load = 10 k and 100 pf. 11 dac differential nonlinearity specified on 0 v to v ref and 0 v to v dd ranges. 12 dac specification for output impedance in the unbuffered case depends on dac code. 13 dac specifications for i sink , voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode . dac in unbuffered mode tested with op 270 external buffer, which has a low input leakage current. 14 measured with c ref pin decoupled with 0.47 f capaci tor to ground. power-up time for the internal reference is determined by the value of the dec oupling capacitor chosen for the c ref pin. 15 when using an external reference device, the internal band gap reference input can be bypassed by setting the adccon1.6 bit. 16 flash/ee memory reliabilit y characteristics apply to bo th the flash/ee pro gram memory and the fl ash/ee data memory. 17 endurance is qualified to 100,000 cycles as per jedec std. 22 metho d a117 and measured at ?40c, +25c, and +85c. typical end urance at 25c is 700,000 cycles. 18 retention lifetime equivalent at junction temperature (t j ) = 55c as per jedec std. 22 method a 117. retention lifetime ba sed on an activa tion energy of 0.6 ev derates with junction temperature as shown in figure 38 in the flash/ee memory reliability section. 19 power supply current consumpt ion is measured in normal, idle, and power-down modes under the following conditions: normal mode: reset = 0.4 v, digital i/o pi ns = open circuit, core clk changed via cd bits in pllcon (a duc842/aduc843), core ex ecuting internal software loop. idle mode: reset = 0.4 v, digital i/o pins = open circuit, co re clk changed via cd bits in pllcon (aduc842/ad uc843), pcon.0 = 1, core execution suspended in idle mode. power-down mode: reset = 0.4 v, all port 0 pins = 0.4 v, all other digital i/o and port 1 pins are open circuit, core clk chang ed via cd bits in pllcon (aduc842/aduc843), pcon.0 = 1, core execution suspended in power-down mode , osc turned on or off v ia osc_pd bit (pllcon.7) in pllcon sfr (a duc842/aduc843). 20 dv dd power supply current increases typically by 3 ma (3 v operation) and 10 ma (5 v operat ion) during a flash/ ee memory program or erase cycle. 21 power supply currents are production tested at 5. 25 v and 3.3 v for a 5 v and 3 v part, respectively.
ADUC841/aduc842/aduc843 rev. 0 | page 8 of 88 absolute maximum ratings table 2. t a = 25c, unless otherwise noted parameter rating av dd to dv dd 0.3 v to +0.3 v agnd to dgnd 0.3 v to +0.3 v dv dd to dgnd, av dd to agnd 0.3 v to +7 v digital input voltage to dgnd 0.3 v to dv dd + 0.3 v digital output voltage to dgnd 0.3 v to dv dd + 0.3 v v ref to agnd 0.3 v to av dd + 0.3 v analog inputs to agnd 0.3 v to av dd + 0.3 v operating temperature range, industrial ADUC841bs,aduc842bs,aduc843bs ADUC841bcp, aduc842bcp, aduc843bcp 40c to +85c storage temperature range 65c to +150c unction temperature 150c ? a thermal impedance (aduc84xbs) 90c/w ? a thermal impedance (aduc84xbcp) 52c/w lead temperature, soldering vapor phase (60 sec) infrared (15 sec) 215c 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test euipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. watchdog timer 256 btes user ram power suppl monitor temp sensor band gap reference av dd agnd dv dd dv dd dv dd dgnd dgnd dgnd reset por sdatamosi miso ss xtal1 ADUC841/aduc842/aduc843 adc control and calibration dac1 dac control 12-bit voltage output dac t0 t1 t2ex t2 int0 int1 ea psen ale single-pin emulator txd rxd 4 kbtes data flash/ee 62 kbtes program flash/ee including user download mode asnchronous serial port (uart) 8052 mcu core downloader debugger snchronous serial interface (i 2 c and spi ) 16-bit counter timers time interval counter (wae-up cct) xtal2 osc 2 kbtes user xram 2 u data pointers 11-bit stac pointer 12-bit voltage output dac mux ... ... 12-bit adc a dc0 a dc1 a dc6 a dc7 dac0 mux 16-bit 6 - dac pwm0 pwm1 16-bit pwm 16-bit pwm pwm control 16-bit 6 - dac t/h c ref buf uart timer scloc 03260-0-002 pll figure 2. aduc block diagram (shaded areas are features not present on the aduc812), no dacs on aduc843, pll on aduc842/aduc843 only.
ADUC841/aduc842/aduc843 rev. 0 | page 9 of 88 pin configurations and functional descriptions 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 p0.7/ad 7 p0.6/ad 6 p0.5/ad 5 p0.4/ad 4 dv dd dgnd p0.3/ad 3 p0.2/ad 2 p0.1/ad1 p0.0/ad 0 ale psen ea p1.7/adc7 reset p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1/miso/pwm1 dv dd p3.4/t0/pwmc/pwm0/extcl p3.5/t1/convst p3.6/wr p3.7/rd scloc p1.0/adc0/t2 p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ss p1.6/adc6 p2.7/pwm1/a15/a23 p2.6/pwm0/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dv dd xtal2 xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi dgnd 03260-0-003 ADUC841/aduc842/aduc843 52-lead pfp extcl not present on the ADUC841 figure 3. 52-lead ppf p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd av dd agnd agnd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ss p1.6/adc6 p.7/adc7 reset p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1/miso/pwm1 dv dd dgnd p3.4/t0/pwmc/pwm0/extcl p3.5/t1/convst p3.6/wr p3.7/rd scloc p2.7/a15/a23 p2.6/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dgnd dv dd xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi p1.0/adc0/t2 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea 14 1 2 3 4 5 6 7 8 9 10 11 13 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 43 45 46 47 48 49 50 51 52 53 54 55 56 pin 1 identifier 44 xtal2 top view (not to scale) 03260-0-004 ADUC841/aduc842/aduc843 56-lead csp extcl not present on the ADUC841 figure 4. 56-lead csp table 3. pin function descriptions mnemonic type function dv dd p digital positive supply voltage. 3 v or 5 v nominal. av dd p analog positive supply voltage. 3 v or 5 v nominal. c ref i/o decoupling input for on-chip reference. conn ect a 0.47 f capacitor between this pin and agnd. v ref nc not connected. this was refe rence out on the aduc812; the c ref pin should be used instead. agnd g analog ground. ground refere nce point for the analog circuitry. p1.0p1.7 i port 1 is an 8-bit input port only. unlike other ports, port 1 defaults to analog inp ut mode. to configure any of these port pins as a digital input, write a 0 to the port bit. adc0adc7 i analog inputs. eight single-ended anal og inputs. channel selection is via adccon2 sfr. t2 i timer 2 digital input. input to timer/co unter 2. when enabled, counter 2 is incremented in response to a 1-to-0 transition of the t2 input. t2ex i digital input. capture/reload trigger for counter 2; also functions as an up/down control input for counter 2. ss i slave select input for the spi interface. sdata i/o user selectable, i 2 c compatible, or spi da ta input/output pin. scloc i/o serial clock pin for i 2 c compatible or for spi serial interface clock. mosi i/o spi master output/slave inp ut data i/o pin for spi interface. miso i/o spi master input/slave output da ta i/o pin for spi serial interface. dac0 o voltage output from dac0. this pin is a no connect on the aduc843. dac1 o voltage output from dac1. this pin is a no connect on the aduc843. reset i digital input. a high level on this pin for 24 master clock cycles while the os cillator is running resets the device.
ADUC841/aduc842/aduc843 rev. 0 | page 10 of 88 mnemonic type function p3.0?p3.7 i/o port 3 is a bidirectional port with internal pull-up resistors. port 3 pins that have 1s wr itten to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inp uts, port 3 pins being pulled externally low source current because of the internal pull-up resistors. port 3 pins also contain various secondary functions, which are described below. pwmc i pwm clock input. pwm0 o pwm0 voltage output. pwm outp uts can be configured to use ports 2.6 and 2.7 or ports 3.4 and 3.3. pwm1 o pwm1 voltage output. see the cfg841/ cfg842 register for further information. rxd i/o receiver data input (asynchr onous) or data input/output (synchro nous) of the serial (uart) port. txd o transmitter data output (async hronous) or clock output (synchrono us) of the serial (uart) port. int0 i interrupt 0. programmable edge or level triggered inte rrupt input; can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 0. int1 i interrupt 1. programmable edge or level triggered inte rrupt input; can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 1. t0 i timer/counter 0 input. t1 i timer/counter 1 input. convst i active low convert start logic input for the adc block when the external convert star t function is enabled. a low-to-high transition on this inp ut puts the track-and-hold into hold mode and starts the conversion. extclk i input for external clock signal. has to be enabled via the cfg842 register. wr o write control signal, logic output. latches the data byte from port 0 into th e external data memory. rd o read control signal, logic output. enable s the external data memory to port 0. xtal2 o output of the inverting oscillator amplifier. xtal1 i input to the invert ing oscillator amplifier. dgnd g digital ground. ground reference point for the digital circuitry. p2.0?p2.7 (a8?a15) (a16?a23) i/o port 2 is a bidirectional port with internal pull-up resistors. port 2 pins that have 1s wr itten to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inp uts, port 2 pins being pulled externally low source current because of the internal pu ll-up resistors. port 2 emits the middle and high-order address bytes during accesses to the extern al 24-bit external data memory space. psen o program store enable, logic output. this pin re mains low during internal program execution. psen is used to enable serial download mode when pulled low through a resistor on power-up or reset. on reset this pin will momentarily become an input and the sta tus of the pin is sampled. if there is no pulldown resistor in place the pin will go momentarilly high and then user code will execute. if a pull-down resistor is in place, the embedded serial download/debug kernel will execute. ale o address latch enable, logic output. this output is used to latch the low b yte and page byte for 24-bit address space accesses of the address into external data memory. ea i external access enable, logic input. wh en held high, this input enables the device to fetch code from internal program memory locations. the parts do not support external code memory. this pin should not be left floating. p0.7?p0.0 (a0-a7) i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pi ns that have 1s written to th em float, and in that state can be used as high impedance inputs . port 0 is also the multiplexed low-order address and data bus during accesses to external data memory. in this application, it uses stro ng internal pull-ups when emitting 1s. types: p = power, g = ground, i= input, o = output., nc = no connect
ADUC841/aduc842/aduc843 rev. 0 | page 11 of 88 terminology adc specifications integral nonlinearity the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point lsb below the first code transition, and full scale, a point lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adacent codes in the adc. offset error the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., + lsb. gain error the deviation of the last code transition from the ideal ain voltage (full scale lsb) after the offset error has been adusted out. signal-to-(noise + distortion) ratio the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling freuency (f s /2), excluding dc. the ratio depends on the number of uantization levels in the digitization process; the more levels, the smaller the uantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to-(noise + distortion) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adusting for zero error and full-scale error. voltage output settling time the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse the amount of charge inected into the analog output when the inputs change state. it is specified as the area of the glitch in nv-sec.
ADUC841/aduc842/aduc843 rev. 0 | page 12 of 88 typical performance characteristics the typical performance plots presented in this section illustrate typical performance of the ADUC841/aduc842/ aduc843 under various operating conditions. figure 5 and figure 6 show typical adc integral nonlinearity (inl) errors from adc code 0 to code 4095 at 5 v and 3 v supplies, respectively. the adc is using its internal reference (2.5 v) and is operating at a sampling rate of 152 khz; the typical worst-case errors in both plots are just less than 0.3 lsb. figure 7 and figure 8 also show adc inl at a higher sampling rate of 400 khz. figure 9 and figure 10 show the variation in worst-case positive (wcp) inl and worst-case negative (wcn) inl versus external reference input voltage. figure 11 and figure 12 show typical adc differential nonlinearity (dnl) errors from adc code 0 to code 4095 at 5 v and 3 v supplies, respectively. the adc is using its internal reference (2.5 v) and is operating at a sampling rate of 152 khz; the typical worst-case errors in both plots are just less than 0.2 lsb. figure 13 and figure 14 show the variation in worst- case positive (wcp) dnl and worst-case negative (wcn) dnl versus external reference input voltage. figure 15 shows a histogram plot of 10,000 adc conversion results on a dc input with v dd = 5 v. the plot illustrates an excellent code distribution pointing to the low noise performance of the on-chip precision adc. figure 16 shows a histogram plot of 10,000 adc conversion results on a dc input for v dd = 3 v. the plot again illustrates a very tight code distribution of 1 lsb with the majority of codes appearing in one output pin. figure 17 and figure 18 show typical fft plots for the parts. these plots were generated using an external clock input. the adc is using its internal reference (2.5 v), sampling a full-scale, 10 khz sine wave test tone input at a sampling rate of 149.79 khz. the resulting ffts shown at 5 v and 3 v supplies illustrate an excellent 100 db noise floor, 71 db signal-to-noise ratio (snr), and thd greater than ?80 db. figure 19 and figure 20 show typical dynamic performance versus external reference voltages. again, excellent ac perform- ance can be observed in both plots with some roll-off being observed as v ref falls below 1 v. figure 21 shows typical dynamic performance versus sampling frequency. snr levels of 71 db are obtained across the sampling range of the parts. figure 22 shows the voltage output of the on-chip temperature sensor versus temperature. although the initial voltage output at 25c can vary from part to part, the resulting slope of ?1. 4 mv/c is constant across all parts. adc codes ?1.0 0 511 lsbs 1023 2047 2559 3071 ?0.8 1535 3583 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 av dd / dv dd = 5v f s = 152khz 4095 03260-0-005 figure 5. typical inl error, v dd = 5 v, f s = 152 khz adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 ?0.2 ?0.6 ?1.0 0.8 0.4 0 ?0.4 ?0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz 03260-0-006 figure 6. typical inl error, v dd = 3 v, f s = 152 khz
ADUC841/aduc842/aduc843 rev. 0 | page 13 of 88 adc codes ?1.0 0 511 lsbs 1023 2047 2559 3071 ?0.8 1535 3583 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 av dd /dv dd = 5v f s = 400khz cd = 4 4095 03260-0-098 figure 7. typical inl error, v dd = 5 v, f s = 400 khz adc codes ?1.0 0 511 lsbs 1023 2047 2559 3071 ?0.8 1535 3583 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 av dd /dv dd = 3v f s = 400khz cd = 4 4095 03260-0-099 figure 8. typical inl error, v dd = 3 v, f s = 400 khz external reference (v) 1.2 wcp?inl (lsbs) 0.8 0.4 0 ?0.4 ?0.6 1.0 0.6 0.2 ?0.2 av dd /dv dd = 5v f s = 152khz 0.5 1.0 1.5 2.0 2.5 5.0 0.6 0.4 0 ?0.4 ?0.6 0.2 ?0.2 wcn?inl (lsbs) wcn inl wcp inl 03260-0-007 figure 9. typical worst-case inl error vs. v ref , v dd = 5 v external reference (v) wcp?inl (lsbs) 0.8 0.4 0 ?0.4 ?0.8 0.6 0.2 ?0.2 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 wcn?inl (lsbs) ?0.6 0.8 0.4 0 ?0.4 ?0.8 0.6 0.2 ?0.2 ?0.6 3.0 2.0 1.0 wcn inl wcp inl 03260-0-008 figure 10. typical worst-case inl error vs. v ref , v dd = 3 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 ?0.2 ?0.6 ?1.0 0.8 0.4 0 ?0.4 ?0.8 3071 3583 0 4095 av dd /dv dd = 5v f s = 152khz 03260-0-009 figure 11. typical dnl error, v dd = 5 v adc codes 1.0 511 1023 1535 2047 2559 lsbs 0.6 0.2 ?0.2 ?0.6 ?1.0 0.8 0.4 0 ?0.4 ?0.8 3071 3583 0 4095 av dd /dv dd = 3v f s = 152khz 03260-0-010 figure 12. typical dnl error, v dd = 3 v
ADUC841/aduc842/aduc843 rev. 0 | page 14 of 88 external reference (v) ?0.6 0.5 wcp?dnl (lsbs) 1.0 2.0 2.5 5.0 ?0.4 1.5 ?0.2 0 0.2 0.4 0.6 wcn?dnl (lsbs) ?0.4 ?0.6 ?0.2 0 0.2 0.4 0.6 av dd /dv dd = 5v f s = 152khz wcp dnl wcn dnl 03260-0-011 figure 13. typical worst-case dnl error vs. v ref , v dd = 5 v external reference (v) wcp?dnl (lsbs) 0.7 0.5 0.1 ?0.5 ?0.7 0.3 ?0.3 av dd /dv dd = 3v f s = 152khz 0.5 1.0 1.5 2.0 2.5 3.0 wcn?dnl (lsbs) wcp dnl wcn dnl ?0.1 0.7 0.5 0.1 ?0.5 ?0.7 0.3 ?0.3 ?0.1 03260-0-012 figure 14. typical worst-case dnl error vs. v ref , v dd = 3 v code 817 818 819 820 821 10000 occurrence 8000 6000 4000 2000 0 03260-0-013 figure 15. code histogram plot, v dd = 5 v code 10000 817 818 819 820 821 occurrence 8000 6000 4000 2000 0 9000 7000 5000 3000 1000 03260-0-014 figure 16. code histogram plot, v dd = 3 v 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 dbs 20 frequency (khz) 10 070 60 50 40 30 av dd /dv dd = 5v f s = 152khz f in = 9.910khz snr = 71.3db thd = ?88.0db enob = 11.6 03260-0-015 figure 17. dynamic performance at v dd = 5 v 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 dbs 20 frequency (khz) 10 070 60 50 40 30 av dd /dv dd = 3v f s = 149.79khz f in = 9.910khz snr = 71.0db thd = ?83.0db enob = 11.5 03260-0-016 figure 18. dynamic performance at v dd = 3 v
ADUC841/aduc842/aduc843 rev. 0 | page 15 of 88 external reference (v) 50 0.5 snr (dbs) 1.0 2.0 2.5 5.0 55 1.5 60 65 70 75 80 thd (dbs) ?100 ?95 ?90 ?85 ?80 ?75 ?70 av dd /dv dd = 5v f s = 152khz snr thd 03260-0-017 figure 19. typical dynamic performance vs. v ref , v dd = 5 v external reference (v) snr (dbs) 80 75 65 50 70 55 av dd /dv dd = 3v f s = 152khz 0.5 1.5 2.5 thd (dbs) snr thd 60 ?70 ?75 ?85 ?100 ?80 ?95 ?90 1.0 2.0 3.0 03260-0-018 figure 20. typical dynamic performance vs. v ref , v dd = 3 v frequency (khz) 64 92.262 snr (dbs) 119.050 172.620 199.410 226.190 66 145.830 68 70 72 76 80 78 74 62 60 65.476 03260-0-019 300.000 350.000 400.000 av dd /dv dd = 5v figure 21. typical dynamic performance vs. sampling frequency temperature ( q c) 03260-0-100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?40 25 85 voltage av dd /dv dd = 3v slope = ?1.4mv/ q c figure 22. typical temperature sensor output vs. temperature general description ( continued ) the parts also incorporate additional analog functionality with two 12-bit dacs, power supply monitor, and a band gap reference on-chip digital peripherals include two 16-bit - dacs, a dual output 16-bit pwm, a watchdog timer, a time interval counter, three timers/counters, and three serial i/o ports (spi, i 2 c, and uart) on the aduc812 and the aduc832, the i 2 c and spi interfaces share some of the same pins for backwards compatibility, this is also the case for the ADUC841/aduc842/aduc843 however, there is also the option to allow spi operate separately on p33, p34, and p3, while i 2 c uses the standard pins the i 2 c interface has also been enhanced to offer repeated start, general call, and uad addressing on-chip factory firmware supports in-circuit serial download and debug modes (via uart) as well as single-pin emulation mode via the ea pin a functional block diagram of the parts is shown on the first page
ADUC841/aduc842/aduc843 rev. 0 | page 16 of 88 functional description 8052 instruction set table 4 documents the number of clock cycles required for each instruction. most instructions are executed in one or two clock cycles, resulting in a 16 mips peak performance when operating at pllcon = 00h on the aduc842/aduc843. on the ADUC841, 20 mips peak performance is possible with a 20 mhz external crystal. table 4. instructions mnemonic description bytes cycles arithmetic add a,rn add register to a 1 1 add a,@ri add indirect memory to a 1 2 add a,dir add direct byte to a 2 2 add a,data add immediate to a 2 2 addc a,rn add register to a with carry 1 1 addc a,@ri add indirect memory to a with carry 1 2 addc a,dir add direct byte to a with carry 2 2 add a,data add immediate to a with carry 2 2 subb a,rn subtract register from a with borrow 1 1 subb a,@ri subtract indirect memory from a with borrow 1 2 subb a,dir subtract direct from a with borrow 2 2 subb a,data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc @ri increment indirect memory 1 2 inc dir increment direct byte 2 2 inc dptr increment data pointer 1 3 dec a decrement a 1 1 dec rn decrement register 1 1 dec @ri decrement indirect memory 1 2 dec dir decrement direct byte 2 2 mul ab multiply a by b 1 9 div ab divide a by b 1 9 da a decimal adust a 1 2 logic anl a,rn and register to a 1 1 anl a,@ri and indirect memory to a 1 2 anl a,dir and direct byte to a 2 2 anl a,data and immediate to a 2 2 anl dir,a and a to direct byte 2 2 anl dir,data and immediate data to direct byte 3 3 orl a,rn or register to a 1 1 orl a,@ri or indirect memory to a 1 2 orl a,dir or direct byte to a 2 2 orl a,data or immediate to a 2 2 orl dir,a or a to direct byte 2 2 orl dir,data or immediate data to direct byte 3 3 xrl a,rn exclusive-or register to a 1 1 xrl a,@ri exclusive-or indirect memory to a 2 2 xrl a,data exclusive-or immediate to a 2 2 xrl dir,a exclusive-or a to direct byte 2 2
ADUC841/aduc842/aduc843 rev. 0 | page 17 of 88 mnemonic description bytes cycles xrl a,dir exclusive-or indirect memory to a 2 2 xrl dir,#data exclusive-or immediate data to direct 3 3 clr a clear a 1 1 cpl a complement a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 data transfer mov a,rn move register to a 1 1 mov a,@ri move indirect memory to a 1 2 mov rn,a move a to register 1 1 mov @ri,a move a to indirect memory 1 2 mov a,dir move direct byte to a 2 2 mov a,#data move immediate to a 2 2 mov rn,#data move register to immediate 2 2 mov dir,a move a to direct byte 2 2 mov rn, dir move register to direct byte 2 2 mov dir, rn move direct to register 2 2 mov @ri,#data mov dir,@ri mov @ri,dir move immediate to indirect memory move indirect to direct memory move direct to indirect memory 2 2 2 2 2 2 mov dir,dir move direct byte to direct byte 3 3 mov dir,#data move immediat e to direct byte 3 3 mov dptr,#data move immediate to data pointer 3 3 movc a,@a+dptr move code byte relative dptr to a 1 4 movc a,@a+pc move code b yte relative pc to a 1 4 movx a,@ri move external (a8) data to a 1 4 movx a,@dptr move external (a16) data to a 1 4 movx @ri,a move a to ex ternal data (a8) 1 4 movx @dptr,a move a to ex ternal data (a16) 1 4 push dir push direct byte onto stack 2 2 pop dir pop direct byte from stack 2 2 xch a,rn exchange a and register 1 1 xch a,@ri exchange a and indirect memory 1 2 xchd a,@ri exchange a and indirect memory nibble 1 2 xch a,dir exchange a and direct byte 2 2 boolean clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c,bit and direct bit and carry 2 2 anl c,/bit and direct bit inverse to carry 2 2 orl c,bit or direct bit and carry 2 2 orl c,/bit or direct bit inverse to carry 2 2 mov c,bit move direct bit to carry 2 2 mov bit,c move carry to direct bit 2 2
ADUC841/aduc842/aduc843 rev. 0 | page 18 of 88 mnemonic description bytes cycles branching jmp @a+dptr jump indirect relative to dptr 1 3 ret return from subroutine 1 4 reti return from interrupt 1 4 acall addr11 absolute jump to subroutine 2 3 ajmp addr11 absolute ju mp unconditional 2 3 sjmp rel short jump (relative address) 2 3 jc rel jump on carry equal to 1 2 3 jnc rel jump on carry equal to 0 2 3 jz rel jump on accumulator = 0 2 3 jnz rel jump on accumulator not equal to 0 2 3 djnz rn,rel decrement register, jnz relative 2 3 ljmp long jump unconditional 3 4 lcall addr16 long jump to subroutine 3 4 jb bit,rel jump on direct bit = 1 3 4 jnb bit,rel jump on direct bit = 0 3 4 jbc bit,rel jump on direct bit = 1 and clear 3 4 cjne a,dir,rel compare a, direct jne relative 3 4 cjne a,#data,rel compare a, immediate jne relative 3 4 cjne rn,#data,rel compare regi ster, immediate jne relative 3 4 cjne @ri,#data,rel compare indirect, immediate jne relative 3 4 djnz dir,rel decrement direct byte, jnz relative 3 4 miscellaneous nop no operation 1 1 1. one cycle is one clock. 2. cycles of movx instructions are four cycles when they have 0 wait state. cycles of movx instructions are 4 + n cycles when t hey have n wait states. 3. cycles of lcall instruction are three cycles when the lcall instruction comes from interrupt. other single-cycle core features timer operation timers on a standard 802 increment by 1 with each machine cycle on the ADUC841/aduc842/aduc843, one machine cycle is eual to one clock cycle therefore the timers increment at the same rate as the core clock ale the output on the ale pin on a standard 802 part is a clock at 1/6th of the core operating freuency on the ADUC841/ aduc842/aduc843 the ale pin operates as follows for a single machine cycle instruction,ale is high for the first half of the machine cycle and low for the second half the ale output is at the core operating freuency for a two or more machine cycle instruction, ale is high for the first half of the first machine cycle and low for the rest of the machine cycles external memory access there is no support for external program memory access on the parts when accessing external ram, the ewait register may need to be programmed to give extra machine cycles to movx commands this is to account for differing external ram access speeds ewait sfr sfr address 9fh power-on default 00h bit addressable no this special function register (sfr) is programmed with the number of wait states for a movx instruction this value can range from 0h to h
ADUC841/aduc842/aduc843 rev. 0 | page 19 of 88 memory organization the ADUC841/aduc842/aduc843 each contain four different memory blocks: x up to 62 kbytes of on-chip flash/ee program memory x 4 kbytes of on-chip flash/ee data memory x 256 bytes of general-purpose ram x 2 kbytes of internal xram flash/ee program memory the parts provide up to 62 kbytes of flash/ee program mem- ory to run user code the user can run code from this internal memory only unlike the aduc812, where code execution can overflow from the internal code space to external code space once the pc becomes greater than 1fffh, the parts do not support the roll-over from fffh in internal code space to f800h in external code space instead, the 2048 bytes between f800h and ffffh appear as nop instructions to user code this internal code space can be downloaded via the uart serial port while the device is in-circuit 6 kbytes of the program memory can be reprogrammed during run time thus the code space can be upgraded in the field by using a user defined protocol, or it can be used as a data memory this is discussed in more detail in the flash/ee memory section for the 32 kbytes memory model, the top 8 kbytes function as the uload space this is explained in the flash/ee memory section flash/ee data memory 4 kbytes of flash/ee data memory are available to the user and can be accessed indirectly via a group of control registers mapped into the special function register (sfr) area access to the flash/ee data memory is discussed in detail in the flash/ee memory section general-purpose ram the general-purpose ram is divided into two separate memories: the upper and the lower 128 bytes of ram the lower 128 bytes of ram can be accessed through direct or indirect addressing the upper 128 bytes of ram can be accessed only through indirect addressing because it shares the same address space as the sfr space, which can be accessed only through direct addressing the lower 128 bytes of internal data memory are mapped as shown in figure 23 the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 to r the next 16 bytes (128 bits), locations 20h to 2fh above the register banks, form a block of directly addressable bit locations at bit addresses 00h to fh the stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes reset initialies the stack pointer to location 0h and incre- ments it once before loading the stack to start from location 08h, which is also the first register (r0) of register bank 1 thus, if the user needs to use more than one register bank, the stack pointer should be initialied to an area of ram not used for data storage 11 10 01 00 0h 0fh 1h 1fh 2fh fh 00h 08h 10h 18h 20h reset value of stack pointer 30h four banks of eight registers r0 to r bit-addressable (bit addresses) general-purpose area banks selected via bits in psw 03260-0-021 figure 23 lower 128 bytes of internal data memory the parts contain 2048 bytes of internal xram, 192 bytes of which can be configured to an extended 11-bit stack pointer by default, the stack operates exactly like an 802 in that it rolls over from ffh to 00h in the general-purpose ram on the parts, however, it is possible (by setting cfg841 or cfg842) to enable the 11-bit extended stack pointer in this case, the stack rolls over from ffh in ram to 0100h in xram the 11-bit stack pointer is visible in the sp and sph sfrs the sp sfr is located at 81h as with a standard 802 the sph sfr is located at bh the 3 lsbs of this sfr contain the 3 extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer
ADUC841/aduc842/aduc843 rev. 0 | page 20 of 88 upper 1792 bytes of on-chip xram (data + stack for exsp = 1, data only for exsp = 0) 256 bytes of on-chip data ram (data + stack) lower 256 bytes of on-chip xram (data only) 00h ffh 00h 07ffh cfg841.7 = 0 cfg842.7 = 0 100h 03260-0-022 cfg841.7 = 1 cfg842.7 = 1 figure 24. extended stack pointer operation external data memory (external xram) ust like a standard 801 compatible core, the ADUC841/ aduc842/aduc843 can access external data memory by using a movx instruction the movx instruction automatically outputs the various control strobes reuired to access the data memory the parts, however, can access up to 16 mbytes of external data memory this is an enhancement of the 64 kbytes of external data memory space available on a standard 801 compatible core the external data memory is discussed in more detail in the hardware design considerations section internal xram the parts contain 2 kbytes of on-chip data memory this memory, although on-chip, is also accessed via the movx instruction the 2 kbytes of internal xram are mapped into the bottom 2 kbytes of the external address space if the cfg841/cfg842 bit is set otherwise, access to the external data memory occurs ust like a standard 801 when using the internal xram, ports 0 and 2 are free to be used as general- purpose i/o external data memor space (24-bit address space) 000000h ffffffh cfg8410 0 cfg8420 0 external data memor space (24-bit address space) 000000h ffffffh cfg8410 1 cfg8420 0 000ffh 000800h 2 kbtes on-chip xram 03260-0-023 figure 2 internal and external xram special function registers (sfrs) the sfr space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only it provides an interface between the cpu and all on-chip periph- erals a block diagram showing the programming model of the parts via the sfr area is shown in figure 26 all registers, except the program counter (pc) and the four general-purpose register banks, reside in the sfr area the sfr registers include control, configur ation, and data registers, which provide an interface between the cpu and all on-chip peripherals 128-bte special function register area 62-kbte electricall reprogrammable nonvolatile flash/ee program memor 801 compatible core other on-chip peripherals temperature sensor 2 u 12-bit dacs serial i/o wdt psm tic pwm 8-channel 12-bit adc 4-kbte electricall reprogrammable nonvolatile flash/ee data memor 2304 btes ram 03260-0-024 figure 26 programming model
ADUC841/aduc842/aduc843 rev. 0 | page 21 of 88 accumulator sfr (acc) acc is the accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and boolean bit manipulations. the mnemonics for accumulator-specific instructions refer to the accumulator as a. b sfr (b) the b register is used with the acc for multiplication and division operations for other instructions, it can be treated as a general-purpose scratchpad register stack pointer (sp and sph) the sp sfr is the stack pointer and is used to hold an internal ram address that is called the top of the stack the sp register is incremented before data is stored during push and call executions while the stack may reside anywhere in on-chip ram, the sp register is initialied to 0h after a reset, which causes the stack to begin at location 08h as mentioned earlier, the parts offer an extended 11-bit stack pointer the 3 extra bits used to make up the 11-bit stack pointer are the 3 lsbs of the sph byte located at bh data pointer (dptr) the data pointer is made up of three 8-bit registers named dpp (page byte), dph (high byte), and dpl (low byte) these are used to provide memory addresses for internal and external code access and for external data access they may be manipu- lated as a 16-bit register (dptr dph, dpl), although inc dptr instructions automatically carry over to dpp, or as three independent 8-bit registers (dpp, dph, dpl) the parts support dual data pointers refer to the dual data pointer section program status word (psw) the psw sfr contains several bits reflecting the current status of the cpu, as detailed in table sfr address d0h power-on default 00h bit addressable es table 5. psw sfr bit designations bit name description 7 c carry flag. 6 ac auxiliary carry flag. 5 f0 general-purpose flag. 4 rs1 register bank select bits. 3 rs0 rs1 0 0 1 1 rs0 0 1 0 1 selected bank 0 1 2 3 2 ov overflow flag. 1 f1 general-purpose flag. 0 p parity bit. power control sfr (pcon) the pcon sfr contains bits for power-saving options and general-purpose status flags, as shown in table 6 sfr address 8h power-on default 00h bit addressable no table 6. pcon sfr bit designations bit no. name description 7 smod double uart baud rate. 6 seripd i 2 c/spi power-down interrupt enable. 5 int0pd int0 power-down interrupt enable. 4 aleoff disable ale output. 3 gf1 general-purpose flag bit. 2 gf0 general-purpose flag bit. 1 pd power-down mode enable. 0 idl idle mode enable.
ADUC841/aduc842/aduc843 rev. 0 | page 22 of 88 special function register banks all registers except the program counter and the four general- purpose register banks reside in the special function register (sfr) area. the sfr registers include control, configuration, and data registers, which provide an interface between the cpu and other on-chip peripherals. figure 27 shows a full sfr memory map and sfr contents on reset. unoccupied sfr locations are shown dark-shaded in the figure (not used). unoccupied locations in the sfr address space are not implemented, i.e., no register exists at this location. if an unoccupied location is read, an unspecified value is returned. sfr locations reserved for on-chip testing are shown lighter shaded (reserved) and should not be accessed by user software. sixteen of the sfr locations are also bit addressable and denoted by 1 in figure 27, i.e., the bit addressable sfrs are those whose address ends in 0h or 8h. spicon 1 f8h 04h dac0l f9h 00h dac0h fah 00h dac1l fbh 00h dac1h fch 00h daccon fdh 04h reserved b 1 f0h 00h adcofsl 3 f1h 00h adcofsh 3 f2h 20h adcgainl 3 f3h 00h adcga i nh 3 f4h 00h adccon3 f5h 00h reserved i2ccon 1 e8h 00h reserved acc 1 e0h 00h reserved adccon2 1 d8h 00h adcdatal d9h 00h adcdatah dah 00h reserved psw 1 d0h 00h dmal d2h 00h dmah d3h 00h dmap d4h 00h reserved t2con 1 c8h 00h rcap2l cah 00h rcap2h cbh 00h tl2 cch 00h th2 cdh 00h reserved wdcon 1 c0h 10h ip 1 b8h 00h econ b9h 00h edata1 bch 00h edata2 bdh 00h ie 1 a8h 00h ieip2 a9h a0h p2 1 a0h ffh scon 1 98h 00h sbuf 99h 00h i2cdat 9ah 00h not used p1 1, 2 90h ffh not used tcon 1 88h 00h tmod 89h 00h tl0 8ah 00h tl1 8bh 00h th0 8ch 00h th1 8dh 00h p0 1 80h ffh sp 81h 07h dpl 82h 00h dph 83h 00h dpp 84h 00h reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used not used not used p3 1 b0h ffh not used not used spidat f7h 00h adccon1 efh 40h reserved psmcon dfh deh edarl c6h 00h edata3 beh 00h edata4 bfh 00h not used pcon 87h 00h ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits i2csi/mdo efh 0 eeh 0 i2c1o1mco edh 0 ech 0 ebh 0 eah e9h 0 e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits adci dfh 0 dma deh 0 cconv ddh 0 sconv dch 0 cs3 dbh 0 cs2 dah cs1 d9h 0 cs0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rs1 d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre3 c7h 0 pre2 c6h 0 pre1 c5h 0 c4h 1 wdir c3h 0 wds c2h wde c1h 0 wdwr c0h 0 bits psi bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah ti 99h 0 ri 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 ie0 89h 0 it0 88h 0 tcon 88h 00h mnemonic sfr address default value mnemonic default value sfr address these bits are contained in this byte. sfr map key: notes 1 sfrs whose address ends in 0h or 8h are bit addressable. 2 the primary function of port1 is as an analog input port; therefore, to enable the digital secondary functions on these port pins, write a 0 to the corresponding port 1 sfr bit. 3 calibration coefficients are preconfigured on power-up to factory calibrated values. 1 reserved reserved reserved 0 0 0 0 0 0 0 0 0 0 00 11 timecon hthsec sec min hour intval dpcon a1h a2h a3h a4h a5h a6h a7h 00h 00h 00h 00h 00h 00h 00h reserved reserved reserved reserved reserved reserved pwmcon aeh 00h cfg841/ cfg842 afh 00h reserved reserved t3fd t3con 9dh 9eh 00h 00h pwm0l pwm0h pwm1l pwm1h sph 00h 00h 00h 00h 00h b1h b2h b3h b4h b7h reserved reserved reserved chipid c2h xxh edarh c7h 00h i2cgc/mde i2cm reserved pre0 pllcon d7h 53h i2c1o0/mdi i2crs i2ctx i2ci i2cadd 9bh 55h 03260-0-025 i2cadd1 91h 7fh i2cadd2 92h 7fh i2cadd3 93h 7fh figure 27. special function register locations and reset values
ADUC841/aduc842/aduc843 rev. 0 | page 23 of 88 adc circuit information general overview the adc conversion block incorporates a fast, 8-channel, 12-bit, single-supply adc this block provides the user with multichannel mux, track-and-hold, on-chip reference, calibra- tion features, and adc all components in this block are easily configured via a 3-register sfr interface the adc converter consists of a conventional successive approximation converter based around a capacitor dac the converter accepts an analog input range of 0 v to v ref a high precision, 1 ppm, low drift, factory calibrated 2 v reference is provided on-chip an external reference can be connected as described in the voltage reference connections section this external reference can be in the range 1 v to av dd single-step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an external pin timer 2 can also be configured to generate a repetitive trigger for adc conversions the adc may be configured to operate in a dma mode whereby the adc block continuously converts and captures samples to an external ram space without any interaction from the mcu core this automatic capture facility can extend through a 16 mbyte external data memory space the ADUC841/aduc842/aduc843 are shipped with factory programmed calibration coefficients that are automatically downloaded to the adc on power-up, ensuring optimum adc performance the adc core contains internal offset and gain calibration registers that can be hardware calibrated to minimie system errors a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front end adc multiplexer (effectively a 9th adc channel input), facilitating a temperature sensor implementation adc transfer function the analog input range for the adc is 0 v to v ref for this range, the designed code transitions occur midway between successive integer lsb values, ie, 0 lsb, 1 lsb, 2 lsb fs 1 lsb the output coding is straight binary with 1 lsb fs/4096 or 2 v/4096 061 mv when v ref 2 v the ideal input/output transfer characteristic for the 0 v to v ref range is shown in figure 28 output code 111111 111110 111101 111100 000011 000010 000001 000000 0v 1lsb fs 1lsb fs 4096 03260-0-026 figure 28 adc transfer function typical operation once configured via the adccon 13 sfrs, the adc converts the analog input and provides an adc 12-bit result word in the adcdatah/l sfrs the top 4 bits of the adcdatah sfr are written with the channel selection bits to identify the channel result the format of the adc 12-bit result word is shown in figure 29 chid top 4 bits high 4 bits of adc result word low 8 bits of the adc result word adcdatah sfr adcdatal sfr 03260-0-02 figure 29 adc result word format
ADUC841/aduc842/aduc843 rev. 0 | page 24 of 88 adccon1(adc control sfr 1) the adccon1 register controls conversion and acuisition times, hardware conversion modes, and power-down modes as detailed below sfr address efh sfr power-on default 40h bit addressable no table 7. adccon1 sfr bit designations bit no. name description 7 md1 the mode bit selects the active operating mode of the adc. set by the user to power up the adc. cleared by the user to power down the adc. 6 extref set by the user to se lect an external reference. cleared by the user to us e the internal reference. the adc clock divide bits (c1, c0) select the divide ratio for the pll master clock (aduc842/aduc843) or the external crystal (ADUC841) used to ge nerate the adc clock. to ensure correct adc operation, the divider ratio must be chosen to reduce the adc clock to 8.38 mhz or lower. a typical adc conversion reuires 16 adc clocks plus the selected acuisition time. the divider ratio is selected as follows: 5 4 c1 c0 c1 0 0 1 1 c0 0 1 0 1 mcl divider 32 4 (do not use with a cd setting of 0) 8 2 the adc acuisition select bits (a1, a0) select the t ime provided for the input track-and-hold amplifier to acuire the input signal. an acuisition of three or more adc clocks is recommended; clocks are as follows: 3 2 a1 a0 a1 0 0 1 1 a0 0 1 0 1 no. adc clks 1 2 3 4 1 t2c the timer 2 conversion bit (t2c) is set by the user to enable the timer 2 overflow bit to be used as the adc conversion start trigger input. 0 exc the external trigger enable bit (exc) is set by the user to allow the external pin p3.5 ( convst ) to be used as the active low convert start input. this input should be an active low pulse (minimum pulse width 100 ns) at the reuired sample rate.
ADUC841/aduc842/aduc843 rev. 0 | page 25 of 88 adccon2(adc control sfr 2) the adccon2 register controls adc channel selection and conversion modes as detailed below sfr address d8h sfr power-on default 00h bit addressable es table 8. adccon2 sfr bit designations bit no. name description 7 adci adc interrupt bit. set by hardware at the end of a single adc conversi on cycle or at the end of a dma block conversion. cleared by hardware when the pc vecto rs to the adc interrupt service routine . otherwise, the adci bit is cleared by user code. 6 dma dma mode enable bit. set by the user to enable a preconfigured adc dma mode operation. a more detailed de scription of this mode is given in the adc dma mode section. the dma bit is automatically set to 0 at the end of a dma cycle. setting this bit causes the ale output to cease; it will start again wh en dma is started and will op erate correctly after dma is complete. 5 cconv continuous conversion bit. set by the user to initiate the adc in to a continuous mode of conversion. in this mode, the adc starts converting based on the timing and channel configuration already se t up in the adccon sfrs; th e adc automatically starts another conversion once a previous conversion has completed. 4 sconv single conversion bit. set to initiate a single conversion cy cle. the sconv bit is automatically rese t to 0 on completion of the single conversion cycle. 3 2 1 0 cs3 cs2 cs1 cs0 channel selection bits. allow the user to program the adc channel selection under software control. when a conversion is initiated, the converted channel is the one pointed to by these channel selection bits. in dma mode, the channel selection is derived from the channel id written to the external memory. cs3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 cs2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 cs1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 cs0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ch 0 1 2 3 4 5 6 7 temp monitor dac0 dac1 agnd v ref dma stop reuires minimum of 1 s to acuire. only use with internal dac output buffer on. only use with internal dac output buffer on. place in xram location to fi nish dma seuence; refer to the adc dma mode section. all other combinations reserved.
ADUC841/aduc842/aduc843 rev. 0 | page 26 of 88 adccon3(adc control sfr 3) the adccon3 register controls the operation of various calibration modes and also indicates the adc busy status sfr address fh sfr power-on default 00h bit addressable no table 9. adccon3 sfr bit designations bit no. name description 7 bus adc busy status bit. a read-only status bit that is se t during a valid adc conversion or during a calibration cycle. busy is automatically cleared by the core at the end of conversion or calibration. 6 rsvd reserved. this bit should always be written as 0. 5 avgs1 number of average selection bits. this bit selects the number of adc readings th at are averaged during a calibration cycle. 4 avgs0 avgs1 0 0 1 1 avgs0 0 1 0 1 number of averages 15 1 31 63 3 rsvd reserved. this bit should always be written as 0. 2 rsvd this bit should always be written as 1 by the user when performing calibration. 1 tpical calibration type select bit. this bit selects between offset (zero-scale) and gain (full-scale) calibration. set to 0 for offset calibration. set to 1 for gain calibration. 0 scal start calibration cycle bit. when set, this bit starts the selected calibration cycle. it is automatically clea red when the calibration cycle is completed.
ADUC841/aduc842/aduc843 rev. 0 | page 27 of 88 the adc incorporates a successive approximation architecture (sar) involving a charge-sampled input stage. figure 30 shows the equivalent circuit of the analog input section. each adc conversion is divided into two distinct phases, as defined by the position of the switches in figure 30. during the sampling phase (with sw1 and sw2 in the track position), a charge proportional to the voltage on the analog input is developed across the input sampling capacitor. during the conversion phase (with both switches in the hold position), the capacitor dac is adjusted via internal sar logic until the voltage on node a is 0, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor dac. the final digital value contained in the sar is then latched out as the result of the adc conversion. control of the sar and timing of acquisition and sampling modes is handled automatically by built-in adc control logic. acquisition and conversion times are also fully configurable under user control. capacitor dac comparator v ref agnd dac1 dac0 temperature monitor ain7 ain0 32pf agnd ADUC841/aduc842/aduc843 node a sw1 sw2 track track hold hold 200 : 200 : 03260-0-028 figure 30. internal adc structure note that whenever a new input channel is selected, a residual charge from the 32 pf sampling capacitor places a transient on the newly selected input. the signal source must be capable of recovering from this transient before the sampling switches go into hold mode. delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution alleviates this burden from the software design task and ultimately results in a cleaner system implementation. one hardware solution is to choose a very fast settling op amp to drive each analog input. such an op amp would need to fully settle from a small signal transient in less than 300 ns in order to guarantee adequate settling under all software configurations. a better solution, recommended for use with any amplifier, is shown in figure 31. though at first glance the circuit in figure 31 may look like a simple antialias- ing filter, it actually serves no such purpose since its corner frequency is well above the nyquist frequency, even at a 200 khz sample rate. though the r/c does help to reject some incoming high frequency noise, its primary function is to ensure that the transient demands of the adc input stage are met. ain0 ADUC841/ aduc842/ aduc843 10 : 0.1 p f 03260-0-029 figure 31. buffering analog inputs it does so by providing a capacitive bank from which the 32 pf sampling capacitor can draw its charge. its voltage does not change by more than one count (1/4096) of the 12-bit transfer function when the 32 pf charge from a previous channel is dumped onto it. a larger capacitor can be used if desired, but not a larger resistor (for reasons described below). the schottky diodes in figure 31 may be necessary to limit the voltage applied to the analog input pin per the absolute maximum ratings. they are not necessary if the op amp is powered from the same supply as the part since in that case the op amp is unable to generate voltages above v dd or below ground. an op amp of some kind is necessary unless the signal source is very low impedance to begin with. dc leakage currents at the parts? analog inputs can cause measurable dc errors with external source impedances as low as 100 or so. to ensure accurate adc operation, keep the total source impedance at each analog input less than 61 . the table 10 illustrates examples of how source impedance can affect dc accuracy. table 10. source impedance and dc accuracy source impedance error from 1 a leakage current error from 10 a leakage current 61 61 v = 0.1 lsb 610 v = 1 lsb 610 610 v = 1 lsb 6.1 mv = 10 lsb although figure 31 shows the op amp operating at a gain of 1, one can, of course, configure it for any gain needed. also, one can ust as easily use an instrumentation amplifier in its place to condition differential signals. use an amplifier that is capable of delivering the signal (0 v to v ref ) with minimal saturation. some single-supply rail-to-rail op amps that are useful for this purpose are described in table 11. check analog devices website www.analog.com for details on these and other op amps and instrumentation amps.
ADUC841/aduc842/aduc843 rev. 0 | page 28 of 88 table 11. some single-supply op amps op amp model characteristics op281/op481 micropower op191/op291/op491 i/o good up to v dd , low cost op196/op296/op496 i/o to v dd , micropower, low cost op183/op283 high gain-bandwidth product op162/op262/op462 high gbp, micro package ad820/ad822/ad824 fet input, low cost ad823 fet input, high gbp eep in mind that the adcs transfer function is 0 v to v ref , and that any signal range lost to amplifier saturation near ground will impact dynamic range. though the op amps in table 11 are capable of delivering output signals that very closely approach ground, no amplifier can deliver signals all the way to ground when powered by a single supply. therefore, if a negative supply is available, you might consider using it to power the front end amplifiers. if you do, however, be sure to include the schottky diodes shown in figure 31 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. to summarize this section, use the circuit in figure 31 to drive the analog input pins of the parts. voltage reference connections the on-chip 2 v band gap voltage reference can be used as the reference source for the adc and dacs to ensure the accuracy of the voltage reference, you must decouple the c ref pin to ground with a 04 f capacitor, as shown in figure 32 note that this is different from the aduc812/aduc831/aduc832 buffer buffer 04 p f 1 : v ref nc c ref 2v band gap reference ADUC841/aduc842/aduc843 03260-0-030 figure 32 decoupling v ref and c ref if the internal voltage reference is to be used as a reference for external circuitry, the c ref output should be used however, a buffer must be used in this case to ensure that no current is drawn from the c ref pin itself the voltage on the c ref pin is that of an internal node within the buffer block, and its voltage is critical for adc and dac accuracy the parts power up with their internal voltage reference in the off state if an external voltage reference is preferred, it should be connected to the c ref pin as shown in figure 33 bit 6 of the adccon1 sfr must be set to 1 to switch in the external reference voltage to ensure accurate adc operation, the voltage applied to c ref must be between 1 v and av dd in situations where analog input signals are proportional to the power supply (such as in some strain gage applications), it may be desirable to connect the c ref pin directly to av dd operation of the adc or dacs with a reference voltage below 1 v, however, may incur loss of accuracy, eventually resulting in missing codes or non- monotonicity for that reason, do not use a reference voltage lower than 1 v buffer 1 : c ref external voltage reference 1 external 0 internal 01 p f 2v band gap reference ADUC841/aduc842/aduc843 adccon16 v dd 03260-0-031 v ref nc figure 33 using an external voltage reference configuring the adc the parts successive approximation adc is driven by a divided down version of the master clock to ensure adeuate adc operation, this adc clock must be between 400 kh and 838 mh freuencies within this range can be achieved easily with master clock freuencies from 400 kh to well above 16 mh, with the four adc clock divide ratios to choose from for example, set the adc clock divide ratio to 8 (ie, adcclk 16216 mh/8 2 mh) by setting the appropriate bits in adccon1 (adccon1 1, adccon14 0) the total adc conversion time is 1 adc clocks, plus 1 adc clock for synchroniation, plus the selected acuisition time (1, 2, 3, or 4 adc clocks) for the preceding example, with a 3-clock acuisition time, total conversion time is 19 adc clocks (or 90 s for a 2 mh adc clock) in continuous conversion mode, a new conversion begins each time the previous one finishes the sample rate is then simply the inverse of the total conversion time described previously in the preceding example, the continuous conversion mode sample rate is 1103 kh
ADUC841/aduc842/aduc843 rev. 0 | page 29 of 88 if using the temperature sensor as the adc input, the adc should be configured to use an adcclk of mclk/32 and four acquisition clocks. increasing the conversion time on the temperature monitor channel improves the accuracy of the reading. to further improve the accuracy, an external reference with low tempera- ture drift should also be used. adc dma mode the on-chip adc has been designed to run at a maximum conversion speed of 238 s (420 kh sampling rate) when converting at this rate, the ADUC841/aduc842/aduc843 microconverter has 2 s to read the adc result and to store the result in memory for further postprocessing otherwise the next adc sample could be lost in an interrupt driven routine, the microconverter would also have to ump to the adc interrupt service routine, which also increases the time reuired to store the adc results in applications where the parts cannot sustain the interrupt rate, an adc dma mode is provided to enable dma mode, bit 6 in adccon2 (dma) must be set, which allows the adc results to be written directly to a 16 mbyte external static memory sram (mapped into data memory space) without any interaction from the core of the part this mode allows the part to capture a contiguous sample stream at full adc update rates (420 kh) typical dma mode configuration example setting the parts to dma mode consists of the following steps: 1. the adc must be powered down. this is done by ensuring that md1 and md0 are both set to 0 in adccon1. 2. the dma address pointer must be set to the start address of where the adc results are to be written. this is done by writing to the dma mode address pointers dmal, dmah, and dmap. dmal must be written to first, followed by dmah, and then by dmap. 3. the external memory must be preconfigured. this consists of writing the reuired adc channel ids into the top four bits of every second memory location in the external sram, starting at the first address specified by the dma address pointer. because the adc dma mode operates independently from the ADUC841/aduc842/aduc843 core, it is necessary to provide it with a stop command. this is done by duplicating the last channel id to be converted followed by 1111 into the next channel selection field. a typical preconfiguration of external memory is shown in figure 34. 11 1 1 00 1 1 00 1 1 100 0 010 1 00 1 0 00000ah 000000h convert adc ch 2 convert adc ch 5 convert adc ch 3 convert temp sensor stop command repeat last channel for a valid stop condition 03260-0-033 figure 34. typical dma external memory preconfiguration 4. the dma is initiated by writing to the adc sfrs in the following seuence: a. adccon2 is written to enable the dma mode, i.e., mov adccon2, 40h; dma mode enabled. b. adccon1 is written to configure the conversion time and power-up of the adc. it can also enable timer 2 driven conversions or external triggered conversions if reuired. c. adc conversions are initiated. this is done by starting single conversions, starting timer 2, running for timer 2 conversions, or receiving an external trigger. when the dma conversions are complete, the adc interrupt bit, adci, is set by hardware, and the external sram contains the new adc conversion results as shown in figure 35. note that no result is written to the last two memory locations. when the dma mode logic is active, it takes the responsibility of storing the adc results away from both the user and the core logic of the part. as the dma interface writes the results of the adc conversions to external memory, it takes over the external memory interface from the core. thus, any core instructions that access the external memory while dma mode is enabled does not get access to the external memory. the core executes the instructions, and they take the same time to execute, but they cannot access the external memory. 1111 0011 0011 100 0 010 1 0010 00000ah 000000h conversion result for adc ch 2 conversion result for adc ch 5 conversion result for adc ch 3 conversion result for temp sensor stop command no conversion result written here 03260-0-034 figure 35. typical external memory configuration post adc dma operation
ADUC841/aduc842/aduc843 rev. 0 | page 30 of 88 the dma logic operates from the adc clock and uses pipelin- ing to perform the adc conversions and to access the external memory at the same time. the time it takes to perform one adc conversion is called a dma cycle. the actions performed by the logic during a typical dma cycle are shown in figure 36. write adc result converted during previous dma cycle read channel id to be converted during next dma cycle convert channel read during previous dma cycle dma cycle 03260-0-035 figure 36. dma cycle figure 36 shows that during one dma cycle, the following actions are performed by the dma logic: 1. an adc conversion is performed on the channel whose id was read during the previous cycle. 2. the 12-bit result and the channel id of the conversion performed in the previous cycle is written to the external memory. 3. the id of the next channel to be converted is read from external memory. for the previous example, the complete flow of events is shown in figure 36. because the dma logic uses pipelining, it takes three cycles before the first correct result is written out. micro operation during adc dma mode during adc dma mode, the microconverter core is free to continue code execution, including general housekeeping and communication tasks however, note that mcu core accesses to ports 0 and 2 (which of course are being used by the dma con- troller) are gated off during the adc dma mode of operation this means that even though the instruction that accesses the external ports 0 or 2 appears to execute, no data is seen at these external ports as a result note that during dma to the inter- nally contained xram, ports 0 and 2 are available for use the only case in which the mcu can access xram during dma is when the internal xram is enabled and the section of ram to which the dma adc results are being written to lies in an external xram then the mcu can access the internal xram only this is also the case for use of the extended stack pointer the microconverter core can be configured with an interrupt to be triggered by the dma controller when it has finished filling the reuested block of ram with adc results, allowing the service routine for this interrupt to postprocess data without any real-time timing constraints adc offset and gain calibration coefficients the ADUC841/aduc842/ aduc843 have two adc calibration coefficients, one for offset calibration and one for gain calibra- tion both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the special function register (sfr) area the offset calibration coefficient is divided into adcofsh (six bits) and adcofsl (8 bits), and the gain calibration coefficient is divided into adcgainh (6 bits) and adcgainl (8 bits) the offset calibration coefficient compensates for dc offset errors in both the adc and the input signal increasing the offset coefficient compensates for positive offset, and effectively pushes the adc transfer function down decreasing the offset coefficient compensates for negative offset, and effectively pushes the adc transfer function up the maximum offset that can be compensated is typically of v ref , which euates to typically 12 mv with a 2 v reference similarly, the gain calibration coefficient compensates for dc gain errors in both the adc and the input signal increasing the gain coefficient compensates for a smaller analog input signal range and scales the adc transfer function up, effectively increasing the slope of the transfer function decreasing the gain coefficient compensates for a larger analog input signal range and scales the adc transfer function down, effectively decreasing the slope of the transfer function the maximum analog input signal range for which the gain coefficient can compensate is 102 v ref , and the minimum input range is 09 v ref , which euates to typically 2 of the reference voltage calibrating the adc two hardware calibration modes are provided, which can be easily initiated by user software the adccon3 sfr is used to calibrate the adc bit 1 (typical) and cs3 to cs0 (adccon2) set up the calibration modes device calibration can be initiated to compensate for significant changes in operating condition freuency, analog input range, reference voltage, and supply voltages in this calibration mode, offset calibration uses internal agnd selected via adccon2 register bits cs3 to cs0 (1011), and gain calibration uses inter- nal v ref selected by bits cs3 to cs0 (1100) offset calibration should be executed first, followed by gain calibration system calibration can be initiated to compensate for both internal and external system errors to perform system calibration by using an external reference, tie the system ground and reference to any two of the six selectable inputs enable external reference mode (adccon16) select the channel connected to agnd via bits cs3 to cs0 and perform system offset calibration select the channel connected to v ref via bits cs3 to cs0 and perform system gain calibration
ADUC841/aduc842/aduc843 rev. 0 | page 31 of 88 initiating the calibration in code when calibrating the adc using adccon1, the adc must be set up into the configuration in which it will be used the adccon3 register can then be used to set up the device and to calibrate the adc offset and gain mov adccon1,#08ch ; adc on; adcclk set ;to divide by 32,4 ;acquisition clock to c a l i br at e d e v i c e of f s e t : mov adccon2,#0bh ;select internal agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit, ;offset calibration to c a l i br at e d e v i c e g ai n : mov adccon2,#0ch ;select internal v ref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration to calibrate system offset, connect system agnd to an adc channel input (0). mov adccon2,#00h ;select external agnd mov adccon3,#25h ;select offset calibration, ;31 averages per bit to calibrate system gain, connect system v ref to an adc channel input (1). mov adccon2,#01h ;select external v ref mov adccon3,#27h ;select offset calibration, ;31 averages per bit, ;offset calibration the calibration cycle time t cal is calculated by the following equation: acq cal t numav adcclk t u u u 16 14 for an adcclk/fcore divide ratio of 32, t acq = 4 adcclk, and numav = 15, the calibration cycle time is ms t t cal cal 8 4 16 15 524288 / 1 14 u u u in a calibration cycle, the adc busy flag (bit 7), instead of framing an individual adc conversion as in normal mode, goes high at the start of calibration and returns to zero only at the end of the calibration cycle. it can therefore be monitored in code to indicate when the calibration cycle is completed. the following code can be used to monitor the busy signal during a calibration cycle: wait: mov a, adccon3 ;move adccon3 to a jb acc.7, wait ;if bit 7 is set jump to wait else continue nonvolatile flash/ee memory the ADUC841/aduc842/aduc843 incorporate flash/ee memory technology on-chip to provide the user with nonvola- tile, in-circuit, reprogrammable code and data memory space. flash/ee memory is a relatively recent type of nonvolatile memory technology, which is based on a single transistor cell architecture. flash/ee memory combines the flexible in-circuit reprogrammable features of eeprom with the space efficient/ density features of eprom as shown in figure 37. because flash/ee technology is based on a single transistor cell architecture, a flash memory array, such as eprom, can be implemented to achieve the space efficiencies or memory densities required by a given design. like eeprom, flash memory can be programmed in-system at a byte level; it must first be erased, the erase being performed in page blocks. thus, flash memory is often and more correctly referred to as flash/ee memory. eeprom technology eprom technology flash/eememory technology in-circuit reprogrammable s pace efficient / density 03260-0-036 figure 37. flash/ee memory development overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. incorporated in the parts, flash/ee memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (otp) devices at remote operating nodes. flash/ee memory and the ADUC841/aduc842/aduc843 the parts provide two arrays of flash/ee memory for user applications up to 62 kbytes of flash/ee program space are provided on-chip to facilitate code execution without any external discrete rom device reuirements the program memory can be programmed in-circuit by using the serial download mode provided, by using conventional third party memory programmers, or via a user defined protocol that can configure it as data if reuired note that the following sections use the 62 kbyte program space as an example when referring to uload mode for the other memory models (32 kbyte and 8 kbyte), the uload space moves to the top 8 kbytes of the on-chip program memory, ie, for 32 kbytes, the uload space is from 24 kbytes to 32 kbytes, the kernel still resides in a protected space from 60 kbytes to 62 kbytes there is no uload space present on the 8 kbtye part
ADUC841/aduc842/aduc843 rev. 0 | page 32 of 88 a 4 kbyte flash/ee data memory space is also provided on- chip. this may be used as a general-purpose nonvolatile scratchpad area. user access to this area is via a group of six sfrs. this space can be programmed at a byte level, although it must first be erased in 4-byte pages. flash/ee memory reliability the flash/ee program and data memory arrays on the parts are fully ualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention endurance uantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles in real terms, a single endurance cycle is composed of four independ- ent, seuential events, defined as 1 initial page erase seuence 2 read/verify seuence a single flash/ee 3 byte program seuence memory 4 second read/verify seuence endurance cycle in reliability ualification, every byte in both the program and data flash/ee memory is cycled from 00h to ffh until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory as indicated in the specifications table, the parts flash/ee memory endurance ualification has been carried out in accordance with edec retention lifetime specification a11 over the industrial temperature range of 40c to 2c and 2c to 8c the results allow the specification of a mini- mum endurance figure over supply and over temperature of 100,000 cycles, with an endurance figure of 00,000 cycles being typical of operation at 2c retention uantifies the ability of the flash/ee memory to retain its programmed data over time again, the parts have been ualified in accordance with the formal edec retention lifetime specification (a11) at a specific unction temperature (t c) as part of this ualification procedure, the flash/ee memory is cycled to its specified endurance limit, described previously, before data retention is characteried this means that the flash/ee memory is guaranteed to retain its data for its fully specified retention lifetime every time the flash/ee memory is reprogrammed also note that retention lifetime, based on an activation energy of 06 ev, derates with t as shown in figure 38 40 60 0 90 t unction temperature ( c) retention (ears) 20 200 10 100 0 0 0 80 110 300 100 adi specification 100 ears min at t c 03260-0-03 figure 38 flash/ee memory data retention using the flash/ee program memory the 62 kbyte flash/ee program memory array is mapped into the lower 62 kbytes of the 64 kbyte program space addressable by the parts, and is used to hold user code in typical applica- tions the program flash/ee memory array can be programmed in three ways: serial downloading (in-circuit programming) the parts facilitate code download via the standard uart serial port. the parts enter serial download mode after a reset or power cycle if the psen pin is pulled low through an external 1 k resistor. once in serial download mode, the user can download code to the full 62 kbytes of flash/ee program memory while the device is in-circuit in its target application hardware. a pc serial download executable is provided as part of the ADUC841/aduc842 uickstart development system. the serial download protocol is detailed in microconverter application note uc004. parallel programming parallel programming mode is fully compatible with conven- tional third party flash or eeprom device programmers. in this mode, ports p0, p1, and p2 operate as the external data and address bus interface, ale operates as the write enable strobe, and port p3 is used as a general configuration port, which configures the device for various program and erase operations during parallel programming. the high voltage (12 v) supply reuired for flash programming is generated using on-chip charge pumps to supply the high voltage program lines. the complete parallel programming specification is available on the microconverter home page at www.analog.com/microconverter.
ADUC841/aduc842/aduc843 rev. 0 | page 33 of 88 user download mode (uload) figure 39 shows that it is possible to use the 62 kbytes of flash/ee program memory available to the user as a single block of memory. in this mode, all of the flash/ee memory is read-only to user code. however, the flash/ee program memory can also be written to during runtime simply by entering uload mode. in uload mode, the lower 56 kbytes of program memory can be erased and reprogrammed by user software as shown in figure 39 . uload mode can be used to upgrade your code in the field via any user defined download protocol. by configuring the spi port on the part as a slave, it is possible to completely reprogram the 56 kbytes of flash/ee program memory in only 5 seconds (refer to application note uc007). alternatively, uload mode can be used to save data to the 56 kbytes of flash/ee memory. this can be extremely useful in data logging applications where the part can provide up to 60 kbytes of nv data memory on chip (4 kbytes of dedicated flash/ee data memory also exist). the upper 6 kbytes of the 62 kbytes of flash/ee program memory are programmable only via serial download or parallel programming. this means that this space appears as read-only to user code. therefore, it cannot be accidentally erased or reprogrammed by erroneous code execution, which makes it very suitable to use the 6 kbytes as a bootloader. a bootload enable option exists in the serial downloader to always run from e000h after reset. if using a bootloader, this option is recommended to ensure that the bootloader always executes correct code after reset. programming the flash/ee program memory via uload mode is described in more detail in the description of econ and in application note uc007. flash/ee program memory security the ADUC841/aduc842/aduc843 fa cilitate three modes of flash/ee program memory security these modes can be independently activated, restricting access to the internal code space these security modes can be enabled as part of serial download protocol as described in application note uc004 or via parallel programming the security modes available on the parts are as follows: lock mode this mode locks the code memory, disabling parallel program- ming of the program memory. however, reading the memory in parallel mode and reading the memory via a movc command from external memory is still allowed. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. secure mode this mode locks code in memory, disabling parallel program- ming (program and verify/read commands) as well as disabling the execution of a movc instruction from external memory, which is attempting to read the op codes from internal memory. read/write of internal data flash/ee from external memory is also disabled. this mode is deactivated by initiating a code-erase command in serial download or parallel programming modes. serial safe mode this mode disables serial download capability on the device. if serial safe mode is activated and an attempt is made to reset the part into serial download mode, i.e., reset asserted and de- asserted with psen low, the part interprets the serial download reset as a normal reset only. it therefore cannot enter serial download mode but can only execute as a normal reset seuence. serial safe mode can be disabled only by initiating a code-erase command in parallel programming mode.
ADUC841/aduc842/aduc843 rev. 0 | page 34 of 88 using flash/ee data memory the 4 kbytes of flash/ee data memory are configured as 1024 pages, each of 4 bytes. as with the other ADUC841/aduc842/ aduc843 peripherals, the interface to this memory space is via a group of registers mapped in the sfr space. a group of four data registers (edata1?4) is used to hold the four bytes of data at each page. the page is addressed via the two registers, eadrh and eadrl. finally, econ is an 8-bit control register that may be written with one of nine flash/ee memory access commands to trigger various read, write, erase, and verify functions. a block diagram of the sfr interface to the flash/ee data memory array is shown in figure 41. econflash/ee memory control sfr programming of either flash/ee data memory or flash/ ee program memory is done through the flash/ee memory control sfr (econ) this sfr allows the user to read, write, erase, or verify the 4 kbytes of flash/ee data memory or the 6 kbytes of flash/ee program memory bte 1 (0000h) edata1 sfr bte 1 (0004h) bte 1 (0008h) bte 1 (000ch) bte 1 (0ff8h) bte 1 (0ffch) bte 2 (0001h) edata2 sfr bte 2 (000h) bte 2 (0009h) bte 2 (000dh) bte 2 (0ff9h) bte 2 (0ffdh) bte 3 (0002h) edata3 sfr bte 3 (0006h) bte 3 (000ah) bte 3 (000eh) bte 3 (0ffah) bte 3 (0ffeh) bte 4 (0003h) edata4 sfr bte 4 (000h) bte 4 (000bh) bte 4 (000fh) bte 4 (0ffbh) (0fffh) 01h 00h 02h 03h 3feh 3ffh page address (eadrh/l) bte addresses are given in brackets 03260-0-040 bte 4 figure 41 flash/ee data memory control and configuration table 12. econflash/ee memory commands econ value command description (normal mode) (power-on default) command description (uload mode) 01h read results in 4 bytes in the flash/ee data memory, addressed by the page address eadrh/l, being read into edata14. not implemented. use the movc instruction. 02h write results in 4 bytes in edata14 being written to the flash/ee data memory at th e page address given by eadrh/l (0 eadrh/l 0400h). note that the 4 bytes in th e page being addressed must be pre-erased. results in bytes 0255 of internal xram being written to the 256 bytes of flash/ee program memory at the page address given by eadrh (0 eadrh e0h). note that the 256 bytes in th e page being addressed must be pre-erased. 03h reserved. reserved. 04h verif verifies that the data in ed ata14 is contained in the page address given by eadrh/l. a subseuent read of the econ sfr results in 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. not implemented. use the movc and movx instructions to verify the write in software. 05h erase page results in erasing the 4-b yte page of flash/ee data memory addressed by the page address eadrh/l. results in the 64 byte page of flash/ee program memory, addressed by the byte address eadrh/l, being erased. eadrl can eual any of 64 locations within the page. a new page starts whenever eadrl is eual to 00h, 40h, 80h, or c0h. 06h erase all results in erasing the entire 4 kbytes of flash/ee data memory. results in erasing the entire 56 kbytes of uload flash/ee program memory. 81h readbte results in the byte in the flash/ee data memory, addressed by the byte addre ss eadrh/l, being read into edata1 (0 eadrh / l 0fffh). not implemented. use the movc command. 82h writebte results in the byte in edata1 being written into flash/ee data memory at the byte address eadrh/l results in the byte in edata1 being written into flash/ee program memory at the byte address eadrh/l (0 eadrh/l dfffh). 0fh exuload leaves the econ instructions to operate on the flash/ee data memory. enters normal mode dire cting subseuent econ instructions to operate on the flash/ee data memory. f0h uload enters uload mode, directing subseuent econ instructions to operate on the flash/ee program memory. leaves the econ instructions to operate on the flash/ee program memory.
ADUC841/aduc842/aduc843 rev. 0 | page 35 of 88 example: programming the flash/ee data memory a user wants to program f3h into the second byte on page 03h of the flash/ee data memory space while preserving the other 3 bytes already in this page a typical program of the flash/ee data array involves 1 setting eadrh/l with the page address 2 writing the data to be programmed to the edata14 3 writing the econ sfr with the appropriate command step 1: set up the page address address registers eadrh and eadrl hold the high byte address and the low byte address of the page to be addressed. the assembly language to set up the address may appear as mov eadrh,#0 ; set page address pointer mov eadrl,#03h step 2: set up the edata registers write the four values to be written into the page into the four sfrs, edata14. unfortunately, the user does not know three of them. thus, the user must read the current page and over- write the second byte. mov econ,#1 ; read page into edata1-4 mov edata2,#0f3h ; overwrite byte 2 step 3: program page a byte in the flash/ee array can be programmed only if it has previously been erased. to be more specific, a byte can be programmed only if it already holds the value ffh. because of the flash/ee architecture, this erase must happen at a page level; therefore, a minimum of 4 bytes (1 page) are erased when an erase command is initiated. once the page is erase, the user can program the 4 bytes in-page and then perform a verification of the data. mov econ,#5 ; erase page mov econ,#2 ; write page mov econ,#4 ; verify page mov a,econ ; check if econ=0 (ok!) jnz error although the 4 kbytes of flash/ee data memory are shipped from the factory pre-erased, i.e., byte locations set to ffh, it is nonetheless good programming practice to include an eraseall routine as part of any configuration/setup code running on the parts. an eraseall command consists of writing 06h to the econ sfr, which initiates an erase of the 4-kbyte flash/ee array. this command coded in 8051 assembly would appear as mov econ,#06h ; erase all command ; 2 ms duration flash/ee memory timing typical program and erase times for the parts are as follows: normal mode (operating on flash/ee data memory) readpage (4 bytes) 22 machine cycles writepage (4 bytes) 380 s verifpage (4 bytes) 22 machine cycles erasepage (4 bytes) 2 ms eraseall (4 kbytes) 2 ms readbte (1 byte) 9 machine cycles writebte (1 byte) 200 s uload mode (operating on flash/ee program memory) writepage (256 bytes) 16.5 ms erasepage (64 bytes) 2 ms eraseall (56 kbytes) 2 ms writebte (1 byte) 200 s note that a given mode of operation is initiated as soon as the command word is written to the econ sfr. the core micro- controller operation on the parts is idled until the reuested program/read or erase mode is completed. in practice, this means that even though the flash/ee memory mode of operation is typically initiated with a two machine cycle mov instruction (to write to the econ sfr), the next instruction is not executed until the flash/ee operation is complete. this means that the core cannot respond to interrupt reuests until the flash/ee operation is complete, although the core peripheral functions like counter/timers continue to count and time as configured throughout this period.
ADUC841/aduc842/aduc843 rev. 0 | page 36 of 88 aduc842/aduc843 configuration sfr (cfg842) the cfg842 sfr contains the necessary bits to configure the internal xram, external clock select, pwm output selection, dac buffer, and the extended sp for both the aduc842 and the aduc843 by default, it configures the user into 801 mode, ie, extended sp is disabled and internal xram is disabled on the ADUC841, this register is the cfg841 register and is described on the next page cfg842 aduc842/aduc843 config sfr sfr address afh power-on default 00h bit addressable no table 13. cfg842 sfr bit designations bit no. name description 7 exsp extended sp enable. when set to 1 by the user, the stack ro lls over from sph/sp = 00ffh to 0100h. when set to 0 by the user, the stack rolls over from sp = ffh to sp = 00h. 6 pwpo pwm pin out selection. set to 1 by the user to select p3.4 and p3.3 as the pwm output pins. set to 0 by the user to select p2.6 and p2.7 as the pwm output pins. 5 dbuf dac output buffer. set to 1 by the user to by pass the dac output buffer. set to 0 by the user to enable the dac output buffer. 4 extcl set by the user to 1 to sele ct an external clock input on p3.4. set by the user to 0 to use the internal pll clock. 3 rsvd reserved. this bit should always contain 0. 2 rsvd reserved. this bit should always contain 0. 1 mspi set to 1 by the user to move the spi functionalit y of miso, mosi, and scloc to p3.3, p3.4, and p3.5, respectively. set to 0 by the user to leave the spi function ality as usual on miso, mosi, and scloc pins. 0 xramen xram enable bit. when set to 1 by the user, the inte rnal xram is mapped into the lowe r 2 kbytes of the external address space. when set to 0 by the user, the in ternal xram is not a ccessible, and the extern al data memory is mapped into the lower 2 kbytes of external data memory.
ADUC841/aduc842/aduc843 rev. 0 | page 37 of 88 cfg841 ADUC841 config sfr sfr address afh power-on default 10h 1 bit addressable no table 14. cfg841 sfr bit designations bit no. name description 7 exsp extended sp enable. when set to 1 by the user, the stack ro lls over from sph/sp = 00ffh to 0100h. when set to 0 by the user, the stack rolls over from sp = ffh to sp = 00h. 6 pwpo pwm pin out selection. set to 1 by the user to select p3.4 and p3.3 as the pwm output pins. set to 0 by the user to select p2.6 and p2.7 as the pwm output pins. 5 dbuf dac output buffer. set to 1 by the user to by pass the dac output buffer. set to 0 by the user to enable the dac output buffer. 4 epm2 flash/ee controller and pwm clock freuency configuration bits. freuency should be configured such that f osc /divide factor = 32 khz + 50. 3 2 epm1 epm0 epm2 epm1 epm0 divide factor 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 1024 1 mspi set to 1 by the user to move the spi functionalit y of miso, mosi, and scloc to p3.3, p3.4, and p3.5, respectively. set to 0 by the user to leave the spi function ality as usual on miso, mosi, and scloc pins. 0 xramen xram enable bit. when set to 1 by the user, the inte rnal xram is mapped into the lower two kbytes of the external address space. when set to 0 by the user, the intern al xram is not accessib le, and the external data memory is mapped into the lower two kbytes of external data memory. 1 note that the flash/ee controller bits epm2, epm1, epm0 are set to their correct values depending on the crystal freuency at power-up. the user should not modify these bits so all instruction s to the cfg841 register should use the orl, xrl, or anl instructions. va lue of 10h is for 11.05 92 mhz crystal.
ADUC841/aduc842/aduc843 rev. 0 | page 38 of 88 user interface to on-chip peripherals this section gives a brief overview of the various peripherals also available on-chip. a summary of the sfrs used to control and configure these peripherals is also given. dac the ADUC841/aduc842 incorporate two 12-bit voltage output dacs on-chip each has a rail-to-rail voltage output buffer capable of driving 10 k/100 pf each has two selectable ranges, 0 v to v ref (the internal band gap 2 v reference) and 0 v to av dd each can operate in 12-bit or 8-bit mode both dacs share a control register, daccon, and four data registers, dac1h/l, dac0/l note that in 12-bit asynchronous mode, the dac voltage output is updated as soon as the dacl data sfr has been written therefore, the dac data registers should be updated as dach first, followed by dacl note that for correct dac operation on the 0 v to v ref range, the adc must be switched on this results in the dac using the correct reference value daccon dac control register sfr address fdh power-on default 04h bit addressable no table 15. daccon sfr bit designations bit no. name description 7 mode the dac mode bit sets the over riding operating mode for both dacs. set to 1 by the user to select 8-bi t mode (write 8 bits to dacxl sfr). set to 0 by the user to select 12-bit mode. 6 rng1 dac1 range select bit. set to 1 by the user to select the range for dac1 as 0 v to v dd . set to 0 by the user to select the range for dac1 as 0 v to v ref . 5 rng0 dac0 range select bit. set to 1 by the user to select the range for dac0 as 0 v to v dd . set to 0 by the user to select the range for dac0 as 0 v to v ref . 4 clr1 dac1 clear bit. set to 1 by the user to leave the o utput of dac1 at its normal level. set to 0 by the user to forc e the output of dac1 to 0 v. 3 clr0 dac0 clear bit. set to 1 by the user to leave the o utput of dac0 at its normal level. set to 0 by the user to forc e the output of dac0 to 0 v. 2 snc dac0/1 update synchronization bit. when set to 1, the dac outp uts update as soon as dacxl sfrs are wri tten. the user can simultaneously update both dacs by first updating the dacxl/ h sfrs while snc is 0. both dacs then update simultaneously when the snc bit is set to 1. 1 pd1 dac1 power-down bit. set to 1 by the user to power on dac1. set to 0 by the user to power off dac1. 0 pd0 dac0 power-down bit. set to 1 by the user to power on dac0. set to 0 by the user to power off dac0. dacxh/l dac data registers function dac data registers, written by the user to update the dac output. sfr address dac0l (dac0 data low byte) - f9h; dac1l (dac1 data low byte) - fbh dach (dac0 data high byte) - fah; dac1h (dac1 data high byte) - fch power-on default 00h all four registers. bit addressable no all four registers. the 12-bit dac data should be written into dacxh/l right-ustified such that dacxl contains the lower 8 bits, and the lower nib ble of dacxh contains the upper 4 bits.
ADUC841/aduc842/aduc843 rev. 0 | page 39 of 88 using the dac the on-chip dac architecture consists of a resistor string dac followed by an output buffer amplifier, the functional euivalent of which is illustrated in figure 42 details of the actual dac architecture can be found in us patent number 9696 (wwwusptogov) features of this architecture include inherent guaranteed monotonicity and excellent differential linearity output buffer high disable (from mcu) dac0 r r r r r ADUC841/aduc842 av dd v ref 03260-0-041 figure 42 resistor string dac functional euivalent as shown in figure 42, the reference source for each dac is user selectable in software it can be either av dd or v ref in 0 v-to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin in 0 v-to-v ref mode, the dac output transfer function spans from 0 v to the internal v ref or, if an external reference is applied, the voltage at the c ref pin the dac output buffer amplifier features a true rail-to-rail output stage implementation this means that unloaded, each output is capable of swinging to within less than 100 mv of both avdd and ground moreover, the dacs linearity specifica- tion (when driving a 10 k resistive load to ground) is guaranteed through the full transfer function except codes 0 to 100, and, in 0 v-to-avdd mode only, codes 399 to 409 linearity degrada- tion near ground and v dd is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 43 the dotted line in figure 43 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier note that figure 43 represents a transfer function in 0 v-to-v dd mode only in 0 v-to-v ref mode (with v ref v dd ), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the ideal line right to the end (v ref in this case, not v dd ), showing no signs of endpoint linearity errors v dd v dd 0mv v dd 100mv 100mv 0mv 0mv 000h fffh 03260-0-042 figure 43 endpoint nonlinearities due to amplifier saturation source/sink current (ma) 0 10 1 output voltage (v) 4 3 2 1 0 dac loaded with 0000h dac loaded with 0fffh 03260-0-043 figure 44 source and sink current capability with v ref v dd v source/sink current (ma) 4 0 10 1 output voltage (v) 3 1 0 dac loaded with 0000h dac loaded with 0fffh 03260-0-044 figure 4 source and sink current capability with v ref v dd 3 v
ADUC841/aduc842/aduc843 rev. 0 | page 40 of 88 the endpoint nonlinearities illustrated in figure 43 become worse as a function of output loading. most of the part?s specifications assume a 10 k resistive load to ground at the dac output. as the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of figure 43 become larger. larger current demands can sig- nificantly limit output voltage swing. figure 44 and figure 45 illustrate this behavior. note that the upper trace in each of these figures is valid only for an output range selection of 0 v-to-av dd . in 0 v-to-v ref mode, dac loading does not cause high-side voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. for example, if av dd = 3 v and v ref = 2.5 v, the high-side voltage is not be affected by loads less than 5 ma. but somewhere around 7 ma, the upper curve in figure 45 drops below 2.5 v (v ref ), indicating that at these higher currents the output is not capable of reaching v ref . to reduce the effects of the saturation of the output amplifier at values close to ground and to give reduced offset and gain errors, the internal buffer can be bypassed. this is done by setting the dbuf bit in the cfg841/cfg842 register. this allows a full rail-to-rail output from the dac, which should then be buffered externally using a dual-supply op amp in order to get a rail-to- rail output. this external buffer should be located as close as physically possible to the dac output pin on the pcb. note that the unbuffered mode works only in the 0 v to v ref range. to drive significant loads with the dac outputs, external buffering may be required (even with the internal buffer enabled), as illustrated in figure 46 . table 11 lists some recommended op amps. ADUC841/ aduc842 dac0 dac1 03260-0-045 figure 46. buffering the dac outputs the dac output buffer also features a high impedance disable function. in the chips default power-on state, both dacs are disabled, and their outputs are in a high impedance state (or three-state) where they remain inactive until enabled in software. this means that if a zero output is desired during power-up or power-down transient conditions, then a pull- down resistor must be added to each dac output. assuming this resistor is in place, the dac outputs remain at ground potential whenever the dac is disabled.
ADUC841/aduc842/aduc843 rev. 0 | page 41 of 88 on-chip pll the aduc842 and aduc843 are intended for use with a 32.768 khz watch crystal. a pll locks onto a multiple (512) of this to provide a stable 16.78 mhz clock for the system. the ADUC841 operates directly from an external crystal. the core can operate at this frequency or at binary submultiples of it to allow power saving in cases where maximum core performance is not required. the default core clock is the pll clock divided by 8 or 2.097152 mhz. the adc clocks are also derived from the pll clock, with the modulator rate being the same as the crystal oscillator frequency. the preceding choice of frequencies ensures that the modulators and the core are synchronous, regardless of the core clock rate. the pll control register is pllcon. at 5 v the core clock can be set to a maximum of 16.78 mhz, while at 3 v the maximum core clock setting is 8.38 mhz. the cd bits should not be set to 0 on a 3 v part. note that on the ADUC841, changing the cd bits in pllcon causes the core speed to change. the core speed is crystal freq/ 2 cd . the other bits in pllcon are reserved in the case of the ADUC841 and should be written with 0. pllcon pll control register sfr address d7h power-on default 53h bit addressable no table 16. pllcon sfr bit designations bit no. name description 7 oscpd oscillator power-down bit. set by the user to halt the 32 khz oscillator in power-down mode. cleared by the user to enable the 32 khz oscillator in power-down mode. this feature allows the tic to contin ue counting even in power-down mode. 6 loc pll lock bit. this is a read-only bit. set automatically at power-on to indicate that the pll loop is correctly tracking the crystal clock. if the external crystal subseuently becomes disconnected, the pll will rail. cleared automatically at power-o n to indicate that the pll is not correctly tracking the crys tal clock. this may be due to the absence of a crystal clock or an external crystal at power-on. in this mode, the pll output can be 16.78 mhz 20. 5 ---- reserved. should be written with 0. 4 ---- reserved. should be written with 0. 3 fint fast interrupt response bit. set by the user enabling the response to any interrupt to be executed at the fastest core clock freuency, regardless of the configuration of the cd20 bits (see below). once us er code has returned from an interrupt, the core resumes code execution at the core clock selected by the cd20 bits. cleared by the user to disable the fast interrupt response feature. 2 cd2 cpu (core clock) divider bits. 1 cd1 this number determines the freuency at which the microcontroller core operates. 0 cd0 cd2 0 0 0 0 1 1 1 1 cd1 0 0 1 1 0 0 1 1 cd0 0 1 0 1 0 1 0 1 core clock freuency (mhz) 16.777216 8.388608 4.194304 2.097152 (default core clock freuency) 1.048576 0.524288 0.262144 0.131072
ADUC841/aduc842/aduc843 rev. 0 | page 42 of 88 pulse-width modulator (pwm) the pwm on the ADUC841/aduc842/aduc843 is a highly flexible pwm offering programmable resolution and an input clock, and can be configured for any one of six different modes of operation. two of these modes allow the pwm to be config- ured as a - dac with up to 16 bits of resolution. a block diagram of the pwm is shown in figure 47. note the pwm clock?s sources are different for the ADUC841, and are given in table 17. clock select programmable divider compare mode pwm0h/l pwm1h/l f vco to/external pwm clock f xtal /15 f xtal p2.6 p2.7 16-bit pwm counter 03260-0-046 figure 47. pwm block diagram the pwm uses five sfrs: the control sfr (pwmcon) and four data sfrs (pwm0h, pwm0l, pwm1h, and pwm1l). pwmcon, as described in the following sections, controls the different modes of operation of the pwm as well as the pwm clock frequency. pwm0h/l and pwm1h/l are the data registers that deter- mine the duty cycles of the pwm outputs. the output pins that the pwm uses are determined by the cfg841/cfg842 register, and can be either p2.6 and p2.7 or p3.4 and p3.3. in this section of the data sheet, it is assumed that p2.6 and p2.7 are selected as the pwm outputs. to use the pwm user software, first write to pwmcon to select the pwm mode of operation and the pwm input clock. writing to pwmcon also resets the pwm counter. in any of the 16-bit modes of operation (modes 1, 3, 4, 6), user software should write to the pwm0l or pwm1l sfrs first. this value is written to a hidden sfr. writing to the pwm0h or pwm1h sfrs updates both the pwmxh and the pwmxl sfrs but does not change the outputs until the end of the pwm cycle in progress. the values written to these 16-bit registers are then used in the next pwm cycle. pwmcon pwm control sfr sfr address aeh power-on default 00h bit addressable no table 17. pwmcon sfr bit designations bit no. name description 7 sngl turns off pmw output at p2.6 or p3.4 , leaving the port pin free for digital i/o. 6 md2 pwm mode bits. 5 md1 the md2/1/0 bits choose the pwm mode as follows: md2 md1 md0 mode 0 0 0 mode 0: pwm disabled 0 0 1 mode 1: single variable resolution pwm on p2.7 or p3.3 0 1 0 mode 2: twin 8-bit pwm 0 1 1 mode 3: twin 16-bit pwm 1 0 0 mode 4: dual nrz 16-bit - dac 1 0 1 mode 5: dual 8-bit pwm 1 1 0 mode 6: dual rz 16-bit - dac 4 md0 1 1 1 reserved 3 cdiv1 pwm clock divider. scale the clock source for the pwm counter as follows: cdiv1 cdiv0 description 0 0 pwm counter = selected clock/1 0 1 pwm counter = selected clock/4 1 0 pwm counter = selected clock/16 2 cdiv0 1 1 pwm counter = selected clock/64 1 csel1 pwm clock divider. select the clock source for the pwm as follows: csel1 csel0 description 0 0 pwm clock = f xtal /15, ADUC841 = f ocs /divide factor /15 (see the cfg841 register) 0 1 pwm clock = f xtal , ADUC841 = f ocs /divide factor (see the cfg841 register) 1 0 pwm clock = external input at p3.4/t0 0 csel0 1 1 pwm clock = f vco = 16.777216 mhz, ADUC841 = f osc
ADUC841/aduc842/aduc843 rev. 0 | page 43 of 88 pwm modes of operation mode 0: pwm disabled the pwm is disabled allowing p2.6 and p2.7 to be used as normal. mode 1: single variable resolution pwm in mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the pwm to be variable. pwm1h/l sets the period of the output waveform. reducing pwm1h/l reduces the resolution of the pwm output but increases the maximum output rate of the pwm. for example, setting pwm1h/l to 65536 gives a 16-bit pwm with a maxi- mum output rate of 266 hz (16.777 mhz/65536). setting pwm1h/l to 4096 gives a 12-bit pwm with a maximum output rate of 4096 hz (16.777 mhz/4096). pwm0h/l sets the duty cycle of the pwm output waveform, as shown in figure 48. p2.7 pwm counter pwm1h/l 0 pwm0h/l 03260-0-047 figure 48. pwm in mode 1 mode 2: twin 8-bit pwm in mode 2, the duty cycle of the pwm outputs and the resolu- tion of the pwm outputs are both programmable. the maximum resolution of the pwm output is 8 bits. pwm1l sets the period for both pwm outputs. typically, this is set to 255 (ffh) to give an 8-bit pwm, although it is possible to reduce this as necessary. a value of 100 could be loaded here to give a percentage pwm, i.e., the pwm is accurate to 1. the outputs of the pwm at p2.6 and p2.7 are shown in figure 49. as can be seen, the output of pwm0 (p2.6) goes low when the pwm counter euals pwm0l. the output of pwm1 (p2.7) goes high when the pwm counter euals pwm1h and goes low again when the pwm counter euals pwm0h. setting pwm1h to 0 ensures that both pwm outputs start simultaneously. p2.7 p2.6 pwm counter pwm1h 0 pwm1l pwm0h pwm0l 03260-0-048 figure 49. pwm mode 2 mode 3: twin 16-bit pwm in mode 3, the pwm counter is fixed to count from 0 to 65536, giving a fixed 16-bit pwm. operating from the 16.777 mhz core clock results in a pwm output rate of 256 hz. the duty cycle of the pwm outputs at p2.6 and p2.7 is independently programmable. as shown in figure 50, while the pwm counter is less than pwm0h/l, the output of pwm0 (p2.6) is high. once the pwm counter euals pwm0h/l, pwm0 (p2.6) goes low and remains low until the pwm counter rolls over. similarly, while the pwm counter is less than pwm1h/l, the output of pwm1 (p2.7) is high. once the pwm counter euals pwm1h/l, pwm1 (p2.7) goes low and remains low until the pwm counter rolls over. in this mode, both pwm outputs are synchronized, i.e., once the pwm counter rolls over to 0, both pwm0 (p2.6) and pwm1 go high. p2.7 p2.6 pwm counter pwm1h/l 0 65536 pwm0h/l 03260-0-049 figure 50. pwm mode 3
ADUC841/aduc842/aduc843 rev. 0 | page 44 of 88 mode 4: dual nrz 16-bit -? dac mode 4 provides a high speed pwm output similar to that of a -? dac. typically, this mode is used with the pwm clock eual to 16.777216 mhz. in this mode, p2.6 and p2.7 are updated every pwm clock (60 ns in the case of 16 mhz). over any 65536 cycles (16-bit pwm) pwm0 (p2.6) is high for pwm0h/l cycles and low for (65536 pwm0h/l) cycles. similarly, pwm1 (p2.7) is high for pwm1h/l cycles and low for (65536 pwm1h/l) cycles. for example, if pwm1h is set to 4010h (slightly above one uarter of fs), then typically p2.7 will be low for three clocks and high for one clock (each clock is approximately 60 ns). over every 65536 clocks, the pwm compensates for the fact that the output should be slightly above one uarter of full scale by having a high cycle followed by only two low cycles. 16.777mhz 16-bit 60 p s 0 16-bit 16-bit 16-bit 16-bit 16-bit carr out at p1.0 carr out at p2.7 pwm0h/l = c000h pwm1h/l = 4000h 00 1 000 latch 0 111 11 0 03260-0-050 60 p s figure 51. pwm mode 4 for faster dac outputs (at lower resolution), write 0s to the lsbs that are not reuired. if, for example, only 12-bit perform- ance is reuired, write 0s to the four lsbs. this means that a 12-bit accurate -? dac output can occur at 4.096 khz. similarly writing 0s to the 8 lsbs gives an 8-bit accurate -? dac output at 65 khz. mode 5: dual 8-bit pwm in mode 5, the duty cycle of the pwm outputs and the resolu- tion of the pwm outputs are individually programmable. the maximum resolution of the pwm output is 8 bits. the output resolution is set by the pwm1l and pwm1h sfrs for the p2.6 and p2.7 outputs, respectively. pwm0l and pwm0h sets the duty cycles of the pwm outputs at p2.6 and p2.7, respectively. both pwms have the same clock source and clock divider. p2.7 p2.6 pwm counters pwm1h 0 pwm1l pwm0h pwm0l 03260-0-051 figure 52. pwm mode 5 mode 6: dual rz 16-bit -? dac mode 6 provides a high speed pwm output similar to that of a -? dac. mode 6 operates very similarly to mode 4. however, the key difference is that mode 6 provides return-to-zero (rz) -? dac output. mode 4 provides non-return-to-zero -? dac outputs. the rz mode ensures that any difference in the rise and fall times will not affect the -? dac inl. however, the rz mode halves the dynamic range of the -? dac outputs from 0 vav dd down to 0 vav dd /2. for best results, this mode should be used with a pwm clock divider of 4. if pwm1h is set to 4010h (slightly above one uarter of fs), typically p2.7 will be low for three full clocks (3 60 ns), high for half a clock (30 ns), and then low again for half a clock (30 ns) before repeating itself. over every 65536 clocks, the pwm will compensate for the fact that the output should be slightly above one uarter of full scale by leaving the output high for two half clocks in four. the rate at which this happens depends on the value and degree of compensation reuired. 4mhz 16-bit 240 p s 0 16-bit 16-bit 16-bit 16-bit 16-bit carr out at p2.6 carr out at p2.7 pwm0h/l = c000h pwm1h/l = 4000h 00 1 000 latch 0 111 11 0 240 p s 0, 3/4, 1/2, 1/4, 0 03260-0-052 figure 53. pwm mode 6
ADUC841/aduc842/aduc843 rev. 0 | page 45 of 88 serial peripheral interface (spi) the ADUC841/aduc842/ aduc843 integrate a complete hard- ware serial peripheral interface on-chip. spi is an industry- standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. note that the spi pins are shared with the i 2 c pins. therefore, the user can enable only one interface or the other on these pins at any given time (see spe in table 18). spi can be operated at the same time as the i 2 c interface if the mspi bit in cfg841/cfg8842 is set. this moves the spi outputs (miso, mosi, and sclock) to p3.3, p3.4, and p3.5, respectively). the spi port can be configured for master or slave operation and typically consists of four pins, described in the following sections. miso (master in, slave out data i/o pin) the miso pin is configured as an input line in master mode and as an output line in slave mode the miso line on the master (data in) should be connected to the miso line in the slave device (data out) the data is transferred as byte-wide (8-bit) serial data, msb first mosi (master out, slave in pin) the mosi pin is configured as an output line in master mode and as an input line in slave mode the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in) the data is transferred as byte-wide (8-bit) serial data, msb first sclock (serial clock i/o pin) the master serial clock (sclock) is used to synchronie the data being transmitted and received through the mosi and miso data lines a single data bit is transmitted and received in each sclock period therefore, a byte is transmitted/received after eight sclock periods the sclock pin is configured as an output in master mode and as an input in slave mode in master mode, the bit rate, polarity, and phase of the clock are controlled by the cpol, cpha, spr0, and spr1 bits in the spicon sfr (see table 18) in slave mode, the spicon register must be configured with the phase and polarity (cpha and cpol) of the expected input clock in both master and slave modes, the data is transmitted on one edge of the sclock signal and sampled on the other it is important, therefore, that cpha and cpol are configured the same for the master and slave devices ss (slave select input pin) the ss pin is shared with the adc input to configure this pin as a digital input, the bit must be cleared, eg, clr p1 this line is active low data is received or transmitted in slave mode only when the ss pin is low, allowing the parts to be used in single-master, multislave spi configurations if cpha 1, the ss input may be permanently pulled low if cpha 0, the ss input must be driven low before the first bit in a byte-wide transmission or reception and return high again after the last bit in that byte-wide transmission or reception in spi slave mode, the logic level on the external ss pin can be read via the spr0 bit in the spicon sfr the sfr registers, described in the following tables, are used to control the spi interface
ADUC841/aduc842/aduc843 rev. 0 | page 46 of 88 spicon spi control register sfr address f8h power-on default 04h bit addressable es table 18. spicon sfr bit designations bit no. name description 7 ispi spi interrupt bit. set by the microconverter at the end of each spi transfer. cleared directly by user code or in directly by reading the spidat sfr. 6 wcol write collision error bit. set by the microconverter if spidat is writte n to while an spi transfer is in progress. cleared by user code. 5 spe spi interface enable bit. set by the user to enable the spi interface. cleared by the user to enable the i 2 c pins, this is not reuiredto enable the i 2 c interface if the mspi bit is set in cfg841/cfg842. in this case, the i 2 c interface is automatically enabled. 4 spim spi master/slave mode select bit. set by the user to enable master mo de operation (scloc is an output). cleared by the user to enable slave mode operation (scloc is an input). 3 cpol 1 clock polarity select bit. set by the user if scloc idles high. cleared by the user if scloc idles low. 2 cpha 1 clock phase select bit. set by the user if leading sclo c edge is to transmit data. cleared by the user if trailing sc loc edge is to transmit data. 1 spr1 spi bit rate select bits. 0 spr0 these bits select the scloc rate (bit rate) in master mode as follows: spr1 spr0 selected bit rate 0 0 f osc /2 0 1 f osc /4 1 0 f osc /8 1 1 f osc /16 in spi slave mode, i.e., spim = 0, the logic level on the external ss pin can be read via the spr0 bit. 1 the cpol and cpha bits should both contain the same values for master and slave devices. spidat spi data register function spidat sfr is written by the user to transmit data over the spi interface or read by user code to read data ust received by the spi interface. sfr address f7h power-on default 00h bit addressable no
ADUC841/aduc842/aduc843 rev. 0 | page 47 of 88 using the spi interface depending on the configuration of the bits in the spicon sfr shown in table 18, the ADUC841/aduc842/aduc843 spi interface transmits or receives data in a number of possible modes figure 4 shows all possible spi configurations for the parts, and the timing relationships and synchroniation between the signals involved also shown in this figure is the spi interrupt bit (ispi) and how it is triggered at the end of each byte-wide communication sclock (cpol 1) sclock (cpol 0) (cpha 1) (cpha 0) sample input ispi flag data output ispi flag sample input data output msb bit 6 bit bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit bit 4 bit 3 bit 2 bit 1 lsb ss 03260-0-03 figure 4 spi timing, all modes spi interfacemaster mode in master mode, the sclock pin is always an output and generates a burst of eight clocks whenever user code writes to the spidat register the sclock bit rate is determined by spr0 and spr1 in spicon also note that the ss pin is not used in master mode if the parts need to assert the ss pin on an external slave device, a port digital output pin should be used in master mode, a byte transmission or reception is initiated by a write to spidat eight clock periods are generated via the sclock pin and the spidat byte being transmitted via mosi with each sclock period, a data bit is also sampled via miso after eight clocks, the transmitted byte will be completely transmitted, and the input byte will be waiting in the input shift register the ispi flag will be set automatically, and an interrupt will occur if enabled the value in the shift register will be latched into spidat spi interfaceslave mode in slave mode, sclock is an input the ss pin must also be driven low externally during the byte communication trans- mission is also initiated by a write to spidat in slave mode, a data bit is transmitted via miso, and a data bit is received via mosi through each input sclock period after eight clocks, the transmitted byte will be completely transmitted, and the input byte will be waiting in the input shift register the ispi flag will be set automatically, and an interrupt will occur if enabled the value in the shift register will be latched into spidat only when the transmission/reception of a byte has been completed the end of transmission occurs after the eighth clock has been receiv ed if cpha 1, or when ss returns high if cpha 0
ADUC841/aduc842/aduc843 rev. 0 | page 48 of 88 i 2 c compatible interface the ADUC841/aduc842/aduc843 su pport a fully licensed i 2 c serial interface. the i 2 c interface is implemented as a full hardware slave and software master. sdata is the data i/o pin, and scloc is the serial clock. these two pins are shared with the mosi and scloc pins of the on-chip spi interface. to enable the i 2 c interface, the spi interface must be turned off (see spe in table 18) or the spi interface must be moved to p3.3, p3.4, and p3.5 via the cfg841.1/cfg842.1 bit. application note uc001 describes the operation of this interface as imple- mented and is available from the microconverter website at www.analog.com/microconverter . three sfrs are used to control the i 2 c interface and are described in the following tables. i2ccon i 2 c control register sfr address e8h power-on default 00h bit addressable es table 19. i2ccon sfr bit designations, master mode bit no. name description 7 mdo i 2 c software master data outp ut bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. da ta written to this bit is output on the sdata pin if the data outp ut enable (mde) bit is set. 6 mde i 2 c software master data output en able bit (master mode only). set by the user to enable th e sdata pin as an output (tx). cleared by the user to enable the sdata pin as an input (rx). 5 mco i 2 c software master clock outp ut bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. da ta written to this bit is output on the scloc pin. 4 mdi i 2 c software master data inp ut bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the sdata pin is latched into this bit on scloc if the data output enable (mde) bit is 0. 3 i2cm i 2 c master/slave mode bit. set by the user to enable i 2 c software master mode. cleared by the user to enable i 2 c hardware slave mode. 2 ---- reserved. 1 ---- reserved. 0 ---- reserved. table 20. i2ccon sfr bit designations, slave mode bit no. name description 7 i2csi i 2 c stop interrupt enable bit. set by the user to enable i 2 c stop interrupts. if set, a stop bit that follows a valid start condition generates an interrupt. cleared by the user to disable i 2 c stop interrupts. 6 i2cgc i 2 c general call status bit. set by hardware after receiving a general call address. cleared by the user. 5 i2cid1 i 2 c interrupt decode bits. 4 i2cid0 set by hardware to indicate the source of an i 2 c interrupt. 00 start and matching address. 01 repeated start and matching address. 10 user data. 11 stop after a start and matching address. 3 i2cm i 2 c master/slave mode bit. set by the user to enable i 2 c software master mode. cleared by the user to enable i 2 c hardware slave mode.
ADUC841/aduc842/aduc843 rev. 0 | page 49 of 88 bit no. name description 2 i2crs i 2 c reset bit (slave mode only). set by the user to reset the i 2 c interface. cleared by the user code for normal i 2 c operation. 1 i2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting. cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared automatically when user code reads the i2cdat sfr (see i2cdat below). i2cadd i 2 c address register function holds the first i 2 c peripheral address for the part. it may be overwritten by user code. application note uc001 at www.analog.com/microconverter describes the format of the i 2 c standard 7-bit address in detail. sfr address 9bh power-on default 55h bit addressable no i2cadd1 i 2 c address register function holds the second i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 91h power-on default 7fh bit addressable no i2cadd2 i 2 c address register function holds the third i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 92h power-on default 7fh bit addressable no i2cadd3 i 2 c address register function holds the fourth i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 93h power-on default 7fh bit addressable no i2cdat i 2 c data register function written by the user to transmit data over the i 2 c interface or read by user code to read data ust received by the i 2 c interface. accessing i2cdat automatically clears any pending i 2 c interrupt and the i2ci bit in the i2ccon sfr. user software should access i2cdat only once per interrupt cycle. sfr address 9ah power-on default 00h bit addressable no the main features of the microconverter i 2 c interface are x only two bus lines are reuired: a serial data line (sdata) and a serial clock line (scloc). x an i 2 c master can communicate with multiple slave devices. because each slave device has a uniue 7-bit address, single master/slave relationships can exist at all times even in a multislave environment. x ability to respond to four separate addresses when operating in slave mode.
ADUC841/aduc842/aduc843 rev. 0 | page 50 of 88 x an i 2 c slave can respond to repeated start conditions without a stop bit in between. this allows a master to change direction of transfer without giving up the bus. note that the repeated start is detected only when a slave has previously been configured as a receiver. x on-chip filtering rejects <50 ns spikes on the sdata and the sclock lines to preserve data integrity. dv dd i 2 c master i 2 c slave 1 i 2 c slave 2 03260-0-054 figure 55. typical i 2 c system software master mode the ADUC841/aduc842/aduc843 can be used as i 2 c master devices by configuring the i 2 c peripheral in master mode and writing software to output the data bit by bit this is referred to as a software master master mode is enabled by setting the i2cm bit in the i2ccon register to transmit data on the sdata line, mde must be set to enable the output driver on the sdata pin if mde is set, the sdata pin is pulled high or low depending on whether the mdo bit is set or cleared mco controls the sclock pin and is always configured as an output in master mode in master mode, the sclock pin is pulled high or low depending on the whether mco is set or cleared to receive data, mde must be cleared to disable the output driver on sdata software must provide the clocks by toggling the mco bit and reading the sdata pin via the mdi bit if mde is cleared, mdi can be used to read the sdata pin the value of the sdata pin is latched into mdi on a rising edge of sclock mdi is set if the sdata pin was high on the last rising edge of sclock mdi is clear if the sdata pin was low on the last rising edge of sclock software must control mdo, mco, and mde appropriately to generate the start condition, slave address, acknowledge bits, data bytes, and stop conditions these functions are described in application note uc001 hardware slave mode after reset, the ADUC841/aduc842/aduc843 default to hardware slave mode the i 2 c interface is enabled by clearing the spe bit in spicon (this is not necessary if the mspi bit is set) slave mode is enabled by clearing the i2cm bit in i2ccon the parts have a full hardware slave in slave mode, the i 2 c address is stored in the i2cadd register data received or to be transmitted is stored in the i2cdat register once enabled in i 2 c slave mode, the slave controller waits for a start condition if the part detects a valid start condition, fol- lowed by a valid address, followed by the r/ w bit, the i2ci interrupt bit is automatically set by hardware the i 2 c peripheral generates a core interrupt only if the user has pre-configured the i 2 c interrupt enable bit in the ieip2 sfr as well as the global interrupt bit, ea , in the ie sfr ie, ;enabling i2c interrupts for the aduc842 mov ieip2,#01h ; enable i2c interrupt setb ea an autoclear of the i2ci bit is implemented on the parts so that this bit is cleared automatically on a read or write access to the i2cdat sfr. mov i2cdat, a ; i2ci auto-cleared mov a, i2cdat ; i2ci auto-cleared if for any reason the user tries to clear the interrupt more than once, i.e., access the data sfr more than once per interrupt, then the i 2 c controller will halt. the interface will then have to be reset using the i2crs bit. the user can choose to poll the i2ci bit or to enable the inter- rupt. in the case of the interrupt, the pc counter vectors to 003bh at the end of each complete byte. for the first byte, when the user gets to the i2ci isr, the 7-bit address and the r/ w bit appear in the i2cdat sfr. the i2ctx bit contains the r/ w bit sent from the master. if i2ctx is set, the master is ready to receive a byte. therefore the slave will transmit data by writing to the i2cdat register. if i2ctx is cleared, the master is ready to transmit a byte. there- fore the slave will receive a serial byte. software can interrogate the state of i2ctx to determine whether it should write to or read from i2cdat. once the part has received a valid address, hardware holds sclock low until the i2ci bit is cleared by software. this allows the master to wait for the slave to be ready before transmitting the clocks for the next byte. the i2ci interrupt bit is set every time a complete data byte is received or transmitted, provided it is followed by a valid ack. if the byte is followed by a nack, an interrupt is not generated. the part continues to issue interrupts for each complete data byte transferred until a stop condition is received or the inter- face is reset. when a stop condition is received, the interface resets to a state in which it is waiting to be addressed (idle). similarly, if the interface receives a nack at the end of a sequence, it also returns to the default idle state. the i2crs bit can be used to reset the i 2 c interface. this bit can be used to force the interface back to the default idle state.
ADUC841/aduc842/aduc843 rev. 0 | page 51 of 88 dual data pointer the ADUC841/aduc842/aduc843 incorporate two data pointers. the second data pointer is a shadow data pointer and is selected via the data pointer control sfr (dpcon). dpcon also includes some useful features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. dpcon is described in table 21. dpcon data pointer control sfr sfr address a7h power-on default 00h bit addressable no table 21. dpcon sfr bit designations bit no. name description 7 ---- reserved. 6 dpt data pointer au tomatic toggle enable. cleared by the user to disa ble autoswapping of the dptr. set in user software to enable auto matic toggling of the dptr after each each movx or movc instruction. 5 dp1m1 shadow data pointer mode. these two bits enable extra modes of the shadow data pointers operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the shadow data pointer. 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 4 dp1m0 1 1 dptr lsb is toggled after a movx or movc instruct ion. (this instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 3 dp0m1 main data pointer mode. these two bits enable extra modes of th e main data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 behavior of the main data pointer. 0 0 8052 behavior. 0 1 dptr is post-incremented after a movx or a movc instruction. 1 0 dptr is post-decremented after a movx or movc instruction. 1 1 dptr lsb is toggled after a movx or movc instruction. 2 dp0m0 (this instruction can be useful for movi ng 8-bit blocks to/from 16-bit devices.) 1 ---- this bit is not implemented to allow th e inc dpcon instruction toggle the data pointer without incrementing the rest of the sfr. 0 dpsel data pointer select. cleared by the user to select the main da ta pointer. this means that the contents of this 24-bit register are placed into the three sfrs: dpl, dph, and dpp. set by the user to select the shadow da ta pointer. this means that the contents of a separate 24-bit register appears in the three sfrs: dpl, dph, and dpp. note 1: this is the only place where the main and shadow data pointers are distinguished. everywhere else in this data sheet wherever the dptr is mentioned, operation on the active dptr is implied. note 2: only movc/movx @dptr instructions are relevant above. movc/movx pc/@ri instructions do not cause the dptr to automatically post increment/decrement, and so on. to illustrate the operation of dpcon, the following code copies 256 bytes of code memory at address d000h into xram starting from address 0000h. mov dptr,#0 ; main dptr = 0 mov dpcon,#55h ; select shadow dptr ; dptr1 increment mode, ; dptr0 increment mode ; dptr auto toggling on mov dptr,#0d000h ; shadow dptr = d000h moveloop: clr a movc a,@a+dptr ; get data ; post inc dptr ; swap to main dptr (data) movx @dptr,a ; put acc in xram ; increment main dptr ; swap shadow dptr (code) mov a, dpl jnz moveloop
ADUC841/aduc842/aduc843 rev. 0 | page 52 of 88 power supply monitor as its name suggests, the power supply monitor, once enabled, monitors the dv dd supply on the ADUC841/aduc842/ aduc843. it indicates when any of the supply pins drops below one of two user selectable voltage trip points, 2.93 v and 3.08 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.7 v. monitor function is controlled via the psmcon sfr. if enabled via the ieip2 sfr, the monitor interrupts the core using the psmi bit in the psmcon sfr. this bit is not cleared until the failing power supply has returned above the trip point for at least 250 ms. this monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution does not resume until a safe supply level has been well established. the supply monitor is also protected against spurious glitches triggering the interrupt circuit. note that the 5 v part has an internal por trip level of 4.5 v, which means that there are no usable psm levels on the 5 v part. the 3 v part has a por trip level of 2.45 v, allowing all psm trip points to be used. psmcon power supply monitor control register sfr address dfh power-on default deh bit addressable no table 22. psmcon sfr bit designations bit no. name description 7 ---- reserved. 6 cmpd dv dd comparator bit. this is a read-only bit that dire ctly reflects the state of the dv dd comparator. read 1 indicates that the dv dd supply is above its selected trip point. read 0 indicates that the dv dd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. this bit is set high by the microconverter if either cmpa or cmpd is low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cmpd and/or cmpa return (and remain) high, a 250 ms counter is started. when this counter times out, the psmi in terrupt is cleared. psmi can also be written by the user. however, if either comparator output is low, it is not possible for th e user to clear psmi. 4 tpd1 dv dd trip point selection bits. these bits select the dv dd trip point voltage as follows: tpd1 tpd0 selected dv dd trip point (v) 0 0 reserved 0 1 3.08 1 0 2.93 3 tpd0 1 1 reserved 2 ---- reserved. 1 ---- reserved. 0 psmen power supply monitor enable bit. set to 1 by the user to enable the power supply monitor circuit. cleared to 0 by the user to disabl e the power supply monitor circuit.
ADUC841/aduc842/aduc843 rev. 0 | page 53 of 88 watchdog timer the purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADUC841/ aduc842/aduc843 enter an erroneous state, possibly due to a programming error or electrical noise. the watchdog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled, the watchdog circuit generates a system reset or interrupt (wds) if the user program fails to set the watchdog (wde) bit within a predetermined amount of time (see pre3-0 bits in table 23. the watchdog timer is clocked directly from the 32 khz external crystal on the aduc842/aduc843. on the ADUC841, the watchdog timer is clocked by an internal r/c oscillator at 32 khz 10%. the wdcon sfr can be written only by user software if the double write sequence described in wdwr below is initiated on every write access to the wdcon sfr. wdcon watchdog timer control register sfr address c0h power-on default 10h bit addressable es table 23. wdcon sfr bit designations bit no. name description 7 pre3 watchdog timer prescale bits. 6 pre2 the watchdog timeout period is given by the euation t wd = (2 pre (2 9 / f xtal )) 5 pre1 (0 pre 7; f xtal = 32.768 khz (aduc842/aduc843), or 32khz 10(ADUC841) ) pre3 pre2 pre1 pre0 timeout period (ms) action 0 0 0 0 15.6 reset or interrupt 0 0 0 1 31.2 reset or interrupt 0 0 1 0 62.5 reset or interrupt 0 0 1 1 125 reset or interrupt 0 1 0 0 250 reset or interrupt 0 1 0 1 500 reset or interrupt 0 1 1 0 1000 reset or interrupt 0 1 1 1 2000 reset or interrupt 1 0 0 0 0.0 immediate reset 4 pre0 pre30 1000 reserved 3 wdir watchdog interrupt response enable bit. if this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the watchdog timeout period has expired. this interrupt is not disabled by the clr ea instruction, and it is also a fixed, high priority interrupt. if the watchdog is not being used to monitor the system , it can be used alternatively as a timer. the prescaler is used to set the timeout period in which an interrupt will be generated. 2 wds watchdog status bit. set by the watchdog controller to indica te that a watchdog timeout has occurred. cleared by writing a 0 or by an external hardware reset. it is not cleared by a watchdog reset. 1 wde watchdog enable bit. set by the user to enable the watchdog and clear its counters. if this bit is no t set by the user within the watchdog timeout period, the watchdog generates a reset or interrupt, depending on wdir. cleared under the following conditions: user writes 0, wa tchdog reset (wdir = 0); hardware reset; psm interrupt. watchdog write enable bit. to write data to the wdcon sfr invo lves a double instructio n seuence. the wdwr bit must be set and the very next instruction must be a writ e instruction to the wdcon sfr. for example: clr ea ;disable interrupts while writing ;to wdt setb wdwr ;allow write to wdcon mov wdcon,#72h ;enable wdt for 2.0s timeout 0 wdwr setb ea ;enable interrupts again (if rqd)
ADUC841/aduc842/aduc843 rev. 0 | page 54 of 88 time interval counter (tic) a tic is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. the tic is capable of timeout intervals ranging from 1/128 second to 255 hours. furthermore, this counter is clocked by the external 32.768 khz crystal rather than by the core clock, and it has the ability to remain active in power-down mode and time long power-down intervals. this has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. six sfrs are associated with the time interval counter, timecon being its control register. depending on the configuration of the it0 and it1 bits in timecon, the selected time counter regis- ter overflow clocks the interval counter. when this counter is equal to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. if the part is in power-down mode, again with tic interrupt enabled, the tii bit wakes up the device and resumes code execution by vectoring directly to the tic interrupt service vector address at 0053h. the tic-related sfrs are described in table 24. note also that the time based sfrs can be written initially with the current time; the tic can then be controlled and accessed by user software. in effect, this facilitates the implementation of a real-time clock. a block diagram of the tic is shown in figure 56. the tic is clocked directly from a 32 khz external crystal on the aduc842/aduc843 and by the internal 32 khz 10% r/c oscillator on the ADUC841. due to this, instructions that access the tic registers will also be clocked at this speed. the user should ensure that there is sufficient time between instructions to these registers to allow them to execute correctly. 8-bit prescaler hundredths counter hthsec second counter sec minute counter min hour counter hour tien interval timeout t ime interval counter interrupt 8-bit interval counter timer intval intval interval timebase selection mux tcen 32.768khz external crystal its0, 1 compare count = intval 03260-0-055 figure 56. tic, simplified block diagram
ADUC841/aduc842/aduc843 rev. 0 | page 55 of 88 table 24. timecon sfr bit designations bit no. name description 7 ---- reserved. 6 tfh twenty-four hour select bit. set by the user to enable the hour counter to count from 0 to 23. cleared by the user to enable the ho ur counter to count from 0 to 255. 5 its1 interval timebase selection bits. 4 its0 written by user to determine the interval counter update rate. its1 its0 interval timebase 0 0 1/128 second 0 1 seconds 1 0 minutes 1 1 hours 3 sti single time interval bit. set by the user to generate a single interval t imeout. if set, a timeout clears the tien bit. cleared by the user to allow the interval counter to be automatically reloaded and st art counting again at each interval timeout. 2 tii tic interrupt bit. set when the 8-bit interval counter matches the value in the intval sfr. cleared by user software. 1 tien time interval enable bit. set by the user to enable th e 8-bit time interval counter. cleared by the user to di sable the interval counter. 0 tcen time clock enable bit. set by the user to enable the time clock to the time interval counters. cleared by the user to disable the clock to the time interval counters and rese t the time interval sfrs to the last value written to them by the user. the time registers (h thsec, sec, min, and hour) can be written while tcen is low. timecon tic control register sfr address a1h power-on default 00h bit addressable no
ADUC841/aduc842/aduc843 rev. 0 | page 56 of 88 intval user time interval select register function user code writes the reuired time interval to this register. when the 8-bit interval counter is eual to the time interval value loaded in the intval sfr, the tii bit (timecon.2) is set and generates an interrupt if enabled. sfr address a6h power-on default 00h bit addressable no valid value 0 to 255 decimal hthsec hundredths seconds time register function this register is incremented in 1/128 second intervals once tcen in timecon is active. the hthsec sfr counts from 0 to 127 before rolling over to increment the sec time register. sfr address a2h power-on default 00h bit addressable no valid value 0 to 127 decimal sec seconds time register function this register is incremented in 1-second intervals once tcen in timecon is active. the sec sfr counts from 0 to 59 before rolling over to increment the min time register. sfr address a3h power-on default 00h bit addressable no valid value 0 to 59 decimal min minutes time register function this register is incremented in 1-minute intervals once tcen in timecon is active. the min sfr counts from 0 to 59 before rolling over to increment the hour time register. sfr address a4h power-on default 00h bit addressable no valid value 0 to 59 decimal hour hours time register function this register is incremented in 1-hour intervals once tcen in timecon is active. the hour sfr counts from 0 to 23 before rolling over to 0. sfr address a5h power-on default 00h bit addressable no valid value 0 to 23 decimal
ADUC841/aduc842/aduc843 rev. 0 | page 57 of 88 8052 compatible on-chip peripherals this section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. these remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 sfr bit definitions. parallel i/o the ADUC841/aduc842/aduc843 us e four input/output ports to exchange data with external devices in addition to performing general-purpose i/o, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device in general, when a peripheral is enabled, that pin may not be used as a general-purpose i/o pin port 0 port 0 is an 8-bit open-drain bidirectional i/o port that is directly controlled via the port 0 sfr port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory figure shows a typical bit latch and i/o buffer for a port 0 port pin the bit latch (one bit in the ports sfr) is represented as a type d flip-flop, which clocks in a value from the internal bus in response to a write to latch signal from the cpu the q output of the flip-flop is placed on the internal bus in response to a read latch signal from the cpu the level of the port pin itself is placed on the internal bus in response to a read pin signal from the cpu some instructions that read a port activate the read latch signal, and others activate the read pin signal see the read-modify-write instructions section for details control read latch internal bus write to latch read pin d cl q q latch dv dd addr/data p0x pin 03260-0-06 figure port 0 bit latch and i/o buffer as shown in figure , the output drivers of port 0 pins are switchable to an internal addr and addr/data bus by an internal control signal for use in external memory accesses during external memory accesses, the p0 sfr has 1s written to it, ie, all of its bit latches become 1 when accessing external memory, the control signal in figure goes high, enabling push-pull operation of the output pin from the internal address or data bus (addr/data line) therefore, no external pull-ups are reuired on port 0 for it to access external memory in general-purpose i/o port mode, port 0 pins that have 1s writ- ten to them via the port 0 sfr are configured as open-drain and will therefore float in this state, port 0 pins can be used as high impedance inputs this is represented in figure by the nand gate whose output remains high as long as the control signal is low, thereby disabling the top fet external pull-up resistors are therefore reuired when port 0 pins are used as general-purpose outputs port 0 pins with 0s written to them drive a logic low output voltage (v ol ) and are capable of sinking 16 ma port 1 port 1 is also an 8-bit port directly controlled via the p1 sfr port 1 digital output capability is not supported on this device port 1 pins can be configured as digital inputs or analog inputs by (power-on) default, these pins are configured as analog inputs, ie, 1 written in the corresponding port 1 register bit to configure any of these pins as digital inputs, the user should write a 0 to these port bits to configure the corresponding pin as a high impedance digital input these pins also have various secondary functions as described in table 2 table 25. port 1 alternate pin functions pin no. alternate function p1.0 t2 (timer/counter 2 external input) p1.1 t2ex (timer/counter 2 capture/reload trigger) p1.5 ss (slave select for the spi interface) read latch internal bus write to latch read pin d cl latch p1.x pin to adc 03260-0-057 figure 58. port 1 bit latch and i/o buffer port 2 port 2 is a bidirectional port with internal pull-up resistors directly controlled via the p2 sfr port 2 also emits the high- order address bytes during fetches from external program memory, and middle and high order address bytes during accesses to the 24-bit external data memory space as shown in figure 9, the output drivers of port 2 are switch- able to an internal addr and addr/data bus by an internal control signal for use in external memory accesses (as for port 0) in external memory addressing mode (control 1), the port pins feature push-pull operation controlled by the internal address bus (addr line) however, unlike the p0 sfr during external memory accesses, the p2 sfr remains unchanged
ADUC841/aduc842/aduc843 rev. 0 | page 58 of 88 in general-purpose i/o port mode, port 2 pins that have 1s written to them are pulled high by the internal pull-ups (figure 60) and, in that state, can be used as inputs. as inputs, port 2 pins being pulled externally low source current because of the internal pull-up resistors. port 2 pins with 0s written to them drive a logic low output voltage (v ol ) and are capable of sinking 1.6 ma. p2.6 and p2.7 can also be used as pwm outputs. when they are selected as the pwm outputs via the cfg841/cfg842 sfr, the pwm outputs overwrite anything written to p2.6 or p2.7. control read latch internal bus write to latch read pin d cl q latch dv dd addr p2.x pin dv dd internal pull-up* * see following figure for details of internal pull-up q 03260-0-058 figure 59. port 2 bit latch and i/o buffer from port latch 2 clk delay q1 dv dd q2 dv dd q3 dv dd px.x pin q4 q 03260-0-059 figure 60. internal pull-up configuration port 3 port 3 is a bidirectional port with internal pull-ups directly controlled via the p3 sfr port 3 pins that have 1s written to them are pulled high by the internal pull-ups and, in that state, can be used as inputs as inputs, port 3 pins being pulled externally low source current because of the internal pull-ups port 3 pins with 0s written to them will drive a logic low output voltage (v ol ) and are capable of sinking 4 ma port 3 pins also have various secondary functions as described in table 26 the alternate functions of port 3 pins can be activated only if the corresponding bit latch in the p3 sfr contains a 1 otherwise, the port pin is stuck at 0 table 26. port 3 alternate pin functions pin no. alternate function p3.0 rxd (uart input pin) (or serial data i/o in mode 0) p3.1 txd (uart output pin) (or serial clock output in mode 0) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1)/pwm 1/miso p3.4 t0 (timer/counter 0 external input) pwm external clock/pwm 0 p3.5 t1 (timer/counter 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe) p3.3 and p3.4 can also be used as pwm outputs. when they are selected as the pwm outputs via the cfg841/cfg842 sfr, the pwm outputs overwrite anything written to p3.4 or p3.3. read latch internal bus write to latch read pin d cl latch dv dd p3.x pin internal pull-up see previous figure for details of internal pull-up alternate output function alternate input function 03260-0-060 figure 61. port 3 bit latch and i/o buffer additional digital i/o in addition to the port pins, the dedicated spi/i 2 c pins (sclock and sdata/mosi) also feature both input and output func- tions their euivalent i/o architectures are illustrated in figure 62 and figure 64, respectively, for spi operation and in figure 63 and figure 6 for i 2 c operation notice that in i 2 c mode (spe 0), the strong pull-up fet (q1) is disabled, leaving only a weak pull-up (q2) present by contrast, in spi mode (spe 1) the strong pull-up fet (q1) is controlled directly by spi hardware, giving the pin push-pull capability in i 2 c mode (spe 0), two pull-down fets (q3 and q4) operate in parallel to provide an extra 60 or 0 of current sinking capability in spi mode (spe 1), however, only one of the pull-down fets (q3) operates on each pin, resulting in sink capabilities identical to that of port 0 and port 2 pins on the input path of sclock, notice that a schmitt trigger conditions the signal going to the spi hardware to prevent false triggers (double triggers) on slow incoming edges for incoming signals from the sclock and sdata pins going to i 2 c hardware, a filter conditions the signals to reect glitches of up to 0 ns in duration notice also that direct access to the sclock and sdata/ mosi pins is afforded through the sfr interface in i 2 c master mode therefore, if you are not using the spi or i 2 c functions, you can use these two pins to give additional high current digital outputs q3 schmitt trigger q1 q2 (off) dv dd q4 (off) sclock pin spe 1 (spi enable) hardware spi (master/slave) 03260-0-061 figure 62 sclock pin i/o functional euivalent in spi mode
ADUC841/aduc842/aduc843 rev. 0 | page 59 of 88 mosi is shared with p3.3 and, as such, has the same configuration as the one shown in figure 61. mco i2c m q3 q4 sclock pin q2 q1 (off) dv dd 50ns glitch rejection filter spe = 0 (i 2 c enable) hardware i 2 c (slave only) sfr bits 03260-0-062 figure 63. sclock pin i/o functional equivalent in i 2 c mode q3 q1 q2 (off) dv dd q4 (off) sdata/ mosi pin spe = 1 (spi enable) hardware spi (master/slave) 03260-0-097 figure 64. sdata/mosi pin i/o functional equivalent in spi mode q3 q4 q2 q1 dv dd mco sdata/ mosi pin (off) 50ns glitch rejection filter spe = 0 (i 2 c enable) hardware i 2 c (slave only) sfr bits mci mde i2c m 03260-0-063 figure 65. sdata/mosi pin i/o functional equivalent in i 2 c mode read-modify-write instructions some 801 instructions that read a port read the latch while others read the pin the instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch these are called read-modify- write instructions, which are listed below when the destination operand is a port or a port bit, these instructions read the latch rather than the pin table 27. read-write-modify instructions instruction description anl logical and, e.g., anl p1, a orl (logical or, e.g., orl p2, a xrl (logical ex-or, e.g., xrl p3, a bc ump if bit = 1 and clear bit, e.g., bc p1.1, label cpl complement bit, e.g., cpl p3.0 inc increment, e.g., inc p2 dec decrement, e.g., dec p2 dnz decrement and ump if not zero, e.g., dnz p3, label mov px., c 1 move carry to bit of port x clr px. 1 clear bit of port x setb px. 1 set bit of port x 1 these instructions read the port byte (all 8 bits), modify the addressed bit, and then write the new byte back to the latch. read-modify-write instructions are directed to the latch rather than to the pin to avoid a possible misinterpretation of the voltage level of a pin. for example, a port pin might be used to drive the base of a transistor. when 1 is written to the bit, the transistor is turned on. if the cpu then reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as a logic 0. reading the latch rather than the pin returns the correct value of 1.
ADUC841/aduc842/aduc843 rev. 0 | page 60 of 88 timers/counters the ADUC841/aduc842/ aduc843 have three 16-bit timer/ counters: timer 0, timer 1, and timer 2 the timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software each timer/counter consists of two 8-bit registers: thx and tlx (x 0, 1, and 2) all three can be configured to operate either as timers or as event counters in timer function, the tlx register is incremented every machine cycle thus, one can think of it as counting machine cycles since a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock freuency in counter function, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin: t0, t1, or t2 when the samples show a high in one cycle and a low in the next cycle, the count is incremented since it takes two machine cycles (two core clock periods) to recognie a 1-to-0 transition, the maximum count rate is half the core clock freuency there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle user configuration and control of all timer operating modes is achieved via three sfrs: tmod, tcon control and configuration for timers 0 and 1. t2con control and configuration for timer 2. tmod timer/counter 0 and 1 mode register sfr address 89h power-on default 00h bit addressable no table 28. tmod sfr bit designations bit no. name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while the int1 pin is high and the tr1 control bit is set. cleared by software to enable timer 1 whenever the tr1 control bit is set. 6 c/t timer 1 timer or counter select bit. set by software to select counte r operation (input from t1 pin). cleared by software to select timer opera tion (input from internal system clock). 5 m1 timer 1 mode select bit 1 (used with m0 bit). timer 1 mode select bit 0. m1 m0 0 0 th1 operates as an 8-bit timer/co unter. tl1 serves as 5-bit prescaler. 0 1 16-bit timer/counter. th1 and tl1 ar e cascaded; there is no prescaler. 1 0 8-bit autoreload timer/counter. th1 holds a value that is to be reloaded into tl1 each time it overflows. 4 m0 1 1 timer/counter 1 stopped. 3 gate timer 0 gating control. set by software to enable timer/counter 0 only while the int0 pin is high and the tr0 control bit is set. cleared by software to enable timer 0 whenever the tr0 control bit is set. 2 c/t timer 0 timer or counter select bit. set by software to select counte r operation (input from t0 pin). cleared by software to select timer opera tion (input from internal system clock). 1 m1 timer 0 mode select bit 1. timer 0 mode select bit 0. m1 m0 0 0 th0 operates as an 8-bit timer/coun ter. tl0 serves as a 5-bit prescaler. 0 1 16-bit timer/counter. th0 and tl0 ar e cascaded; there is no prescaler. 1 0 8-bit autoreload timer/counter. th0 holds a value that is to be reloaded into tl0 each time it overflows. 0 m0 1 1 tl0 is an 8-bit timer/counter controlle d by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits.
ADUC841/aduc842/aduc843 rev. 0 | page 61 of 88 tcon timer/counter 0 and 1 control register sfr address 88h power-on default 00h bit addressable es table 29. tcon sfr bit designations bit no. name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by the user to turn on timer/counter 1. cleared by the user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vecto rs to the interrupt service routine. 4 tr0 timer 0 run control bit. set by the user to turn on timer/counter 0. cleared by the user to turn off timer/counter 0. 3 ie1 1 external interrupt 1 (int1 ) flag. set by hardware by a falling edge or by a zero le vel being applied to the external interrupt pin, int1 , depending on the state of bit it1. cleared by hardware when the pc vecto rs to the interrupt service routine on ly if the interrupt was transition- activated. if level-activated, the external reuesting so urce controls the reuest flag, rather than the on-chip hardware. 2 it1 1 external interrupt 1 (ie1) trigger type. set by software to specify edge-sensiti ve detection, i.e., 1-to-0 transition. cleared by software to specify level-s ensitive detection, i.e., zero level. 1 ie0 1 external interrupt 0 (int0 ) flag. set by hardware by a falling edge or by a zero level being applied to external interrupt pin int0 , depending on the state of bit it0. cleared by hardware when the pc vecto rs to the interrupt service routine on ly if the interrupt was transition- activated. if level-activated, the external reuesting so urce controls the reuest flag, rather than the on-chip hardware. 0 it0 1 external interrupt 0 (ie0) trigger type. set by software to specify edge-sensiti ve detection, i.e.,1-to-0 transition. cleared by software to specify level-s ensitive detection, i.e., zero level. 1 these bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the exte rnal int0 and int1 interrupt pins. timer/counter 0 and 1 data registers each timer consists of two 8-bit registers. these can be used as independent registers or combined into a single 16-bit register depending on the timer mode configuration. th0 and tl0 timer 0 high byte and low byte. sfr address = 8ch 8ah, respectively. th1 and tl1 timer 1 high byte and low byte. sfr address = 8dh, 8bh, respectively.
ADUC841/aduc842/aduc843 rev. 0 | page 62 of 88 timer/counter 0 and 1 operating modes the following sections describe the operating modes for timer/counters 0 and 1. unless otherwise noted, assume that these modes of operation are the same for both timer 0 and timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter figure 66 shows mode 0 operation note that the divide-by-12 prescaler is not present on the single-cycle core core clk p34/t0 p32/int0 tr0 tf0 th0 (8 bits) interrupt tl0 ( bits) control gate c/t 1 c/t 0 03260-0-064 figure 66 timer/counter 0, mode 0 in this mode, the timer register is configured as a 13-bit register as the count rolls over from all 1s to all 0s, it sets the timer overflow flag, tf0 tf0 can then be used to reuest an interrupt the counted input is enabled to the timer when tr0 1 and either gate 0 or int0 1 setting gate 1 allows the timer to be controlled by external input int0 to facilitate pulse-width measurements tr0 is a control bit in the special function register tcon gate is in tmod the 13-bit register consists of all 8 bits of th0 and the lower five bits of tl0 the upper 3 bits of tl0 are indeterminate and should be ignored setting the run flag (tr0) does not clear the registers mode 1 (16-bit timer/counter) mode 1 is the same as mode 0, except that the mode 1 timer register is running with all 16 bits mode 1 is shown in figure 6 core clk control p34/t0 gate tr0 tf0 tl0 (8 bits) th0 (8 bits) interrupt p32/in t0 c/ t 0 c/ t 1 03260-0-066 figure 6 timer/counter 0, mode 1 mode 2 (8-bit timer/counter with autoreload) mode 2 configures the timer register as an 8-bit counter (tl0) with automatic reload, as shown in figure 68 overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0, which is preset by software the reload leaves th0 unchanged control tf0 tl0 (8 bits) interrupt reload th0 (8 bits) core clk p34/t0 gate tr0 p32/int0 c/ t 0 c/ t 1 03260-0-06 figure 68 timer/counter 0, mode 2 mode 3 (two 8-bit timer/counters) mode 3 has different effects on timer 0 and timer 1 timer 1 in mode 3 simply holds its count the effect is the same as setting tr1 0 timer 0 in mode 3 establishes tl0 and th0 as two separate counters this configuration is shown in figure 69 tl0 uses the timer 0 control bits: c/ t , gate, tr0, int0 , and tf0 th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1 thus, th0 now controls the timer 1 interrupt mode 3 is provided for applications reuiring an extra 8-bit timer or counter when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or it can still be used by the serial interface as a baud rate generator in fact, it can be used in any application not reuiring an interrupt from timer 1 itself control tf0 tl0 (8 bits) interrupt core clk p34/t0 gate tr0 tf1 th0 (8 bits) interrupt core clk/12 tr1 p32/int0 c/ t 0 c/ t 1 03260-0-068 figure 69 timer/counter 0, mode 3
ADUC841/aduc842/aduc843 rev. 0 | page 63 of 88 table 30. t2con sfr bit designations bit no. name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 cannot be set when either rcl = 1 or tcl = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is ca used by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 rcl receive clock enable bit. set by the user to enable the serial por t to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by the user to enable timer 1 over flow to be used for the receive clock. 4 tcl transmit clock enable bit. set by the user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by the user to enable timer 1 over flow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by the user to enable a capture or reload to occur as a re sult of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by the user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by the user to start timer 2. cleared by the user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by the user to select counter fu nction (input from external t2 pin). cleared by the user to select timer fu nction (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by the user to enable captures on ne gative transitions at t2ex if exen2 = 1. cleared by the user to enable autorelo ads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rcl = 1 or tcl = 1, this bit is ignored an d the timer is forced to auto reload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it these are used as both timer data registers and as timer capture/reload registers th2 and tl2 timer 2, data high byte and low byte. sfr address = cdh, cch, respectively. rcap2h and rcap2l timer 2, capture/reload byte and low byte. sfr address = cbh, cah, respectively. t2con timer/counter 2 control register sfr address c8h power-on default 00h bit addressable es
ADUC841/aduc842/aduc843 rev. 0 | page 64 of 88 timer/counter operating modes the following sections describe the operating modes for timer/counter 2. the operating modes are selected by bits in the t2con sfr, as shown in table 31. table 31. t2con operating modes rcl (or) tcl cap2 tr2 mode 0 0 1 16-bit autoreload 0 1 1 16-bit capture 1 x 1 baud rate x x 0 off 16-bit autoreload mode autoreload mode has two options that are selected by bit exen2 in t2con if exen2 0, then when timer 2 rolls over, it not only sets tf2 but also causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2l and rcap2h, which are preset by software if exen2 1, then timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2 autoreload mode is illustrated in figure 0 16-bit capture mode capture mode also has two options that are selected by bit exen2 in t2con if exen2 0, then timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt if exen2 1, then timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt capture mode is illustrated in figure 1 the baud rate generator mode is selected by rclk 1 and/or tclk 1 in either case, if timer 2 is being used to generate the baud rate, the tf2 interrupt flag will not occur therefore, timer 2 interrupts will not occur, so they do not have to be disabled in this mode, the exf2 flag, however, can still cause interrupts, which can be used as a third external interrupt baud rate generation is described as part of the uart serial port operation in the following section core clk t2 pin c/t2 0 c/t2 1 tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h core clk is defined b the cd bits in pllcon 03260-0-069 figure 0 timer/counter 2, 16-bit autoreload mode tf2 core clk t2 pin tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h c/ t2 0 c/ t2 1 core clk is defined b the cd bits in pllcon 03260-0-00 figure 1 timer/counter 2, 16-bit capture mode
ADUC841/aduc842/aduc843 rev. 0 | page 65 of 88 uart serial interface the serial port is full-duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is complete, the first byte is lost. the physical interface to the serial data network is via pins rxd(p3.0) and txd(p3.1), while the sfr interface to the uart is comprised of sbuf and scon, as described below. sbuf both the serial port receive and transmit registers are accessed through the sbuf sfr (sfr address = 99h). writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. scon uart serial port control register sfr address 98h power-on default 00h bit addressable es table 32. scon sfr bit designations bit no. name description 7 sm0 uart serial mode select bits. these bits select the serial po rt operating mode as follows: sm0 sm1 selected operating mode. 0 0 mode 0: shift register, fi xed baud rate (coreclk/2). 0 1 mode 1: 8-bit uart, variable baud rate. 1 0 mode 2: 9-bit uart, fixed baud rate (coreclk/32) or (coreclk/16). 6 sm1 1 1 mode 3: 9-bit uart, variable baud rate. 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 must be cleared. in mode 1, if sm2 is set, ri is not acti vated if a valid stop bit was not received. if sm2 is cleared, ri is set as soon as the byte of data has been received. in modes 2 or 3, if sm2 is set, ri is not activa ted if the received 9th data bit in rb8 is 0. if sm2 is cleared, ri is set as soon as the byte of data has been received. 4 ren serial port receive enable bit. set by user software to enab le serial port reception. cleared by user software to di sable serial port reception. 3 tb8 serial port transmit (bit 9). the data loaded into tb8 is the 9th da ta bit transmitted in modes 2 and 3. 2 rb8 serial port receiver bit 9. the 9th data bit received in modes 2 and 3 is latched in to rb8. for mode 1, the st op bit is latched into rb8. 1 ti serial port transmit interrupt flag. set by hardware at the end of the 8th bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0 ri serial port receive interrupt flag. set by hardware at the end of the 8th bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software.
ADUC841/aduc842/aduc843 rev. 0 | page 66 of 88 mode 0: 8-bit shift register mode mode 0 is selected by clearing both the sm0 and sm1 bits in the sfr scon serial data enters and exits through rxd txd out- puts the shift clock eight data bits are transmitted or received transmission is initiated by any instruction that writes to sbuf the data is shifted out of the rxd line the 8 bits are transmitted with the least significant bit (lsb) first reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0 when ri is cleared, the data is clocked into the rxd line, and the clock pulses are output from the txd line mode 1: 8-bit uart, variable baud rate mode 1 is selected by clearing sm0 and setting sm1 each data byte (lsb first) is preceded by a start bit (0) and followed by a stop bit (1) therefore, 10 bits are transmitted on txd or are received on rxd the baud rate is set by the timer 1 or timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception) transmission is initiated by writing to sbuf the write to sbuf signal also loads a 1 (stop bit) into the 9th bit position of the transmit shift register the data is output bit by bit until the stop bit appears on txd and the transmit interrupt flag (ti) is automatically set, as shown in figure 2 txd ti ( scon1) start bit d0 d1 d2 d3 d4 d d6 d stop bit set interrupt ie, read for more data 03260-0-02 figure 2 uart serial port transmission, mode 1 reception is initiated when a 1-to-0 transition is detected on rxd assuming a valid start bit is detected, character reception continues the start bit is skipped and the 8 data bits are clocked into the serial port shift register when all 8 bits have been clocked in, the following events occur: x the 8 bits in the receive shift register are latched into sbuf x the 9th bit (stop bit) is clocked into rb8 in scon x the receiver interrupt flag (ri) is set this is the case if, and only if, all of the following conditions are met at the time the final shift pulse is generated: x ri 0 x either sm2 0 or sm2 1 x the received stop bit 1 if any of these conditions is not met, the received frame is irretrievably lost, and ri is not set mode 2: 9-bit uart with fixed baud rate mode 2 is selected by setting sm0 and clearing sm1 in this mode, the uart operates in 9-bit mode with a fixed baud rate the baud rate is fixed at coreclk/32 by default, although by setting the smod bit in pcon, the freuency can be doubled to coreclk/16 eleven bits are transmitted or received: a start bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1) the 9th bit is most often used as a parity bit, although it can be used for anything, including a 9th data bit if reuired to transmit, the 8 data bits must be written into sbuf the 9th bit must be written to tb8 in scon when transmission is initiated, the 8 data bits (from sbuf) are loaded onto the transmit shift register (lsb first) the contents of tb8 are loaded into the 9th bit position of the transmit shift register the transmission starts at the next valid baud rate clock the ti flag is set as soon as the stop bit appears on txd reception for mode 2 is similar to that of mode 1 the 8 data bytes are input at rxd (lsb first) and loaded onto the receive shift register when all 8 bits have been clocked in, the following events occur: x the 8 bits in the receive shift register are latched into sbuf x the 9th data bit is latched into rb8 in scon x the receiver interrupt flag (ri) is set this is the case if, and only if, all of the following conditions are met at the time the final shift pulse is generated: x ri 0 x either sm2 0 or sm2 1 x the received stop bit 1 if any of these conditions is not met, the received frame is irretrievably lost, and ri is not set
ADUC841/aduc842/aduc843 rev. 0 | page 67 of 88 mode 3: 9-bit uart with variable baud rate mode 3 is selected by setting both sm0 and sm1 in this mode, the 801 uart serial port operates in 9-bit mode with a vari- able baud rate determined by either timer 1 or timer 2 the operation of the 9-bit uart is the same as for mode 2, but the baud rate can be varied as for mode 1 in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register reception is initiated in mode 0 by the condition ri 0 and ren 1 reception is initiated in the other modes by the incoming start bit if ren 1 uart serial port baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed. mode 0 baud rate = ( core clock freuency /12) mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/32 of the core clock. if smod = 1, the baud rate is 1/16 of the core clock: mode 2 baud rate = (2 smod /32 core clock freuency ) modes 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the over- flow rate in timer 1 or timer 2, or in both (one for transmit and the other for receive). timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: modes 1 and 3 baud rate (2 smod /32 ( timer 1 overflow rate ) the timer 1 interrupt should be disabled in this application the timer itself can be configured for either timer or counter operation, and in any of its three running modes in the most typical application, it is configured for timer operation in the autoreload mode (high nibble of tmod 0010 binary) in that case, the baud rate is given by the formula modes 1 and 3 baud rate (2 smod /32) ( core clock / 26 ? timer 2 generated baud rates baud rates can also be generated using timer 2 using timer 2 is similar to using timer 1 in that the timer must overflow 16 times before a bit is transmitted/received because timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible using timer 2 modes 1 and 2 baud rate (1/16) ( timer 2 overflow rate ) therefore, when timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before thus, it increments six times faster than timer 1, and therefore baud rates six times faster are possi- ble because timer 2 has 16-bit autoreload capability, very low baud rates are still possible timer 2 is selected as the baud rate generator by setting the tclk and/or rclk in t2con the baud rates for transmit and receive can be simultaneously different setting rclk and/ or tclk puts timer 2 into its baud rate generator mode as shown in figure 3 in this case, the baud rate is given by the formula modes 1 and 3 baud rate ( core clock )/(16 636 ?
ADUC841/aduc842/aduc843 rev. 0 | page 68 of 88 timer 3 generated baud rates the high integer dividers in a uart block mean that high speed baud rates are not always possible using some particular crystals for example, using a 12 mh crystal, a baud rate of 11200 is not possible to address this problem, the part has added a dedicated baud rate timer (timer 3) specifically for generating highly accurate baud rates timer 3 can be used instead of timer 1 or timer 2 for generating very accurate high speed uart baud rates including 11200 and 230400 timer 3 also allows a much wider range of baud rates to be obtained in fact, every desired bit rate from 12 bit/s to 393216 bit/s can be generated to within an error of 08 timer 3 also frees up the other three timers, allowing them to be used for different applications a block diagram of timer 3 is shown in figure 4 (1 t3fd/64) 2 t3 rx/tx clock core clk t3en rx clock tx clock timer 1/timer 2 rx clock fractiona l divider 0 0 1 1 timer 1/timer 2 tx clock 16 2 div 03260-0-04 figure 4 timer 3, uart baud rates two sfrs (t3con and t3fd) are used to control timer 3 t3con is the baud rate control sfr, allowing timer 3 to be used to set up the uart baud rate, and setting up the binary divider (div) the appropriate value to write to the div2-1-0 bits can be calculated using the following formula where f core is defined in pllcon sfr note that the div value must be rounded down 2 log 16 log ? ? 1 ? u rate baud f div core t3fd is the fractional divider ratio required to achieve the required baud rate. the appropriate value for t3fd can be calculated with the following formula: 64 2 2 3 1 u u rate baud f fd t div core note that t3fd should be rounded to the nearest integer. once the values for div and t3fd are calculated, the actual baud rate can be calculated with the following formula: 64 3 2 2 1 u u fd t f rate baud actual div core for example, to get a baud rate of 115200 while operating at 16.7 mhz, i.e., cd = 0 h fd t div 09 9 64 115200 2 / 16777216 2 3 3 18 . 3 2 log / 115200 16 / 16777216 log 2 u u u therefore, the actual baud rate is 114912 bit/s. table 33. t3con sfr bit designations bit no. name description 7 t3bauden t3uartbaud enable. set to enable timer 3 to genera te the baud rate. when set, pcon.7 , t2con.4, and t2con.5 are ignored. cleared to let the baud rate be generated as per a standard 8052. 6 reserved. 5 reserved. 4 reserved. 3 reserved. 2 div2 binary divider factor. 1 div1 div2 div1 div0 bin divider 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 div0 1 1 1 1
ADUC841/aduc842/aduc843 rev. 0 | page 69 of 88 table 34. commonly used baud rates using timer 3 with the 16.777216 mhz pll clock ideal baud cd div t3con t3fd error 230400 0 2 82h 09h 0.25 115200 0 3 83h 09h 0.25 115200 1 2 82h 09h 0.25 115200 2 1 81h 09h 0.25 57600 0 4 84h 09h 0.25 57600 1 3 83h 09h 0.25 57600 2 2 82h 09h 0.25 57600 3 1 81h 09h 0.25 38400 0 4 84h 2dh 0.2 38400 1 3 83h 2dh 0.2 38400 2 2 82h 2dh 0.2 38400 3 1 81h 2dh 0.2 19200 0 5 85h 2dh 0.2 19200 1 4 84h 2dh 0.2 19200 2 3 83h 2dh 0.2 19200 3 2 82h 2dh 0.2 19200 4 1 81h 2dh 0.2 9600 0 6 86h 2dh 0.2 9600 1 5 85h 2dh 0.2 9600 2 4 84h 2dh 0.2 9600 3 3 83h 2dh 0.2 9600 4 2 82h 2dh 0.2 9600 5 1 81h 2dh 0.2
ADUC841/aduc842/aduc843 rev. 0 | page 70 of 88 interrupt system the ADUC841/aduc842/aduc843 pr ovide a total of nine interrupt sources with two priority levels. the control and configuration of the interrupt system is carried out through three interrupt-related sfrs: ie interrupt enable register ip interrupt priority register ieip2 secondary interrupt enable register ie interrupt enable register sfr address a8h power-on default 00h bit addressable es table 35. ie sfr bit designations bit no. name description 7 ea set by the user to enable, or clea red to disable all interrupt sources. 6 eadc set by the user to enable, or cleared to disable adc interrupts. 5 et2 set by the user to enable, or cleared to disable timer 2 interrupts. 4 es set by the user to enable, or cleare d to disable uart serial port interrupts. 3 et1 set by the user to enable, or cl eared to disable 0 timer 1 interrupts. 2 ex1 set by the user to enable, or cl eared to disable exte rnal interrupt 1. 1 et0 set by the user to enable, or cleared to disable timer 0 interrupts. 0 ex0 set by the user to enable, or cl eared to disable external interrupt 0 . ip interrupt priority register sfr address b8h power-on default 00h bit addressable es table 36. ip sfr bit designations bit no. name description 7 ---- reserved. 6 padc written by the user to select the adc interrupt priority (1 = high; 0 = low). 5 pt2 written by the user to select the t imer 2 interrupt priority (1 = high; 0 = low). 4 ps written by the user to select the uart se rial port interrupt priority (1 = high; 0 = low). 3 pt1 written by the user to select the t imer 1 interrupt priority (1 = high; 0 = low). 2 px1 written by the user to select extern al interrupt 1 priority (1 = high; 0 = low). 1 pt0 written by the user to select the t imer 0 interrupt priority (1 = high; 0 = low). 0 px0 written by the user to select extern al interrupt 0 priority (1 = high; 0 = low).
ADUC841/aduc842/aduc843 rev. 0 | page 71 of 88 ieip2 secondary interrupt enable register sfr address a9h power-on default a0h bit addressable no table 37. ieip2 sfr bit designations bit no. name description 7 ---- reserved. 6 pti priority for time interval interrupt. 5 ppsm priority for power supply monitor interrupt. 4 psi priority for spi/i 2 c interrupt. 3 ---- this bit must contain zero. 2 eti set by the user to enable, or cleared to disable time interval counter interrupts. 1 epsmi set by the user to enable, or cleare d to disable power supply monitor interrupts. 0 esi set by the user to enable, or cleared to disable spi or i 2 c serial port interrupts. interrupt priority the interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority regis- ters allow the user to select one of two priority levels for each interrupt an interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt is serviced first an interrupt cannot be interrupted by another interrupt of the same priority level if two interrupts of the same priority level occur simultaneously, a polling seuence is observed as shown in table 38 table 38. priority within an interrupt level source priority description psmi 1 (highest) power supply monitor interrupt. wds 2 watchdog timer interrupt. ie0 2 external interrupt 0. adci 3 adc interrupt. tf0 4 timer/counter 0 interrupt. ie1 5 external interrupt 1. tf1 6 timer/counter 1 interrupt. ispi/i2ci 7 spi interrupt/i 2 c interrupt. ri + ti 8 serial interrupt. tf2 + exf2 9 timer/counter 2 interrupt. tii 11(lowest) time interval counter interrupt. interrupt vectors when an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter the interrupt vector addresses are shown in table 39 table 39. interrupt vector addresses source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h tf2 + exf2 002bh adci 0033h ispi/i2ci 003bh psmi 0043h tii 0053h wds 005bh
ADUC841/aduc842/aduc843 rev. 0 | page 72 of 88 hardware design considerations this section outlines some of the key hardware design considerations that must be addressed when integrating the ADUC841/aduc842/aduc843 into any hardware system. clock oscillator the clock source for the parts can be generated by the internal pll or by an external clock input to use the internal pll, con- nect a 3268 kh parallel resonant crystal between xtal1 and xtal2, and connect a capacitor from each pin to ground as shown in figure the parts contain an internal capacitance of 18 pf on the xtal1 and xtal2 pins, which is sufficient for most watch crystals this crystal allows the pll to lock correctly to give an f vco of 16216 mh if no crystal is present, the pll will free run, giving an fvco of 16 mh 20 in this mode, the cd bits are limited to cd 1, giving a max core clock of 838 mh this is useful if an external clock input is reuired the part powers up and the pll will free run the user then writes to the cfg842 sfr in software to enable the external clock input on p34 note that double the reuired clock must be pro- vided externally since the part runs at cd 1 a better solution is to use the ADUC841 with the external clock for the ADUC841, connect the crystal in the same manner external capacitors should be connected as per the crystal manufacturers recommendations a minimum capacitance of 20 pf is recommended on xtal1 and xtal2 the ADUC841 will not operate if no crystal is present an external clock may be connected as shown in figure 6 and figure xtal2 xtal1 to internal timing circuits ADUC841/aduc842/aduc843 03260-0-06 figure external parallel resonant crystal connections xtal2 xtal1 to internal timing circuits ADUC841 03260-0-0 external clock source figure 6 connecting an external clock source (ADUC841) p34 to internal timing circuits aduc842/aduc843 03260-0-0 external clock source figure connecting an external clock source (aduc842/aduc843) whether using the internal pll or an external clock source, the parts specified operational clock speed range is 400 kh to 16216 mh, (20 mh, ADUC841) the core itself is static, and functions all the way down to dc but at clock speeds slower that 400 kh, the adc can no longer function correctly there- fore, to ensure specified operation, use a clock freuency of at least 400 kh and no more than 20 mh external memory interface in addition to its internal program and data memories, the parts can access up to 16 mbytes of external data memory (sram) note that the parts cannot access external program memory figure 8 shows a hardware configuration for accessing up to 64 kbytes of external ram this interface is standard to any 801 compatible mcu latch sram oe a8a1 a0a d0d (data) ADUC841/ aduc842/ aduc843 rd p2 ale p0 we wr 03260-0-08 figure 8 external data memory interface (64 kbytes address space)
ADUC841/aduc842/aduc843 rev. 0 | page 73 of 88 if access to more than 64 kbytes of ram is desired, a feature unique to the ADUC841/aduc842/aduc843 allows address- ing up to 16 mbytes of external ram simply by adding an additional latch as illustrated in figure 79. latch p2 ale p0 latch sram a8?a15 a0?a7 d0?d7 (data) a16?a23 oe rd we wr ADUC841/ aduc842/ aduc843 03260-0-079 figure 79. external data memory interface (16 mbytes address space) in either implementation, port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the data pointer (dpl) as an address, which is latched by a pulse of ale prior to data being placed on the bus by the ADUC841/aduc842/aduc843 (write operation) or by the sram (read operation). port 2 (p2) provides the data pointer page byte (dpp) to be latched by ale, followed by the data pointer high byte (dph). if no latch is connected to p2, dpp is ignored by the sram, and the 8051 standard of 64 kbytes external data memory access is maintained. power supplies the operational power supply voltage of the parts depends on whether the part is the 3 v version or the v version the specifications are given for power supplies within 2 v to 36 v or of the nominal v level note that figure 80 and figure 81 refer to the pqfp package for the csp package, connect the extra dv dd , dgnd, av dd , and agnd in the same manner also, the paddle on the bottom of the package should be soldered to a metal plate to provide mechanical stability this metal plate should not be connected to ground separate analog and digital power supply pins (av dd and dv dd , respectively) allow av dd to be kept relatively free of the noisy digital signals that are often present on the system dv dd line however, though you can power av dd and dv dd from two separate supplies if desired, you must ensure that they remain within 03 v of one another at all times to avoid damaging the chip (as per the absolute maximum ratings section) therefore, it is recommended that unless av dd and dv dd are connected directly together, back-to-back schottky diodes should be con- nected between them, as shown in figure 80 dv dd agnd av dd 01 p f 10 p f analog suppl 10 p f dgnd 01 p f digital suppl ADUC841/ aduc842/ aduc843 03260-0-080 figure 80 external dual-supply connections as an alternative to providing two separate power supplies, the user can help keep av dd uiet by placing a small series resistor and/or ferrite bead between it and dv dd , and then decoupling av dd separately to ground an example of this configuration is shown in figure 81 with this configuration, other analog circuitry (such as op amps and voltage reference) can be powered from the av dd supply line as well the user will still want to include back-to-back schottky diodes between av dd and dv dd to protect them from power-up and power-down transient conditions that could momentarily separate the two supply voltages dv dd agnd av dd dgnd digital suppl bead 16 : 01 p f 01 p f 10 p f 10 p f ADUC841/ aduc842/ aduc843 03260-0-081 figure 81 external single-supply connections notice that in both figure 80 and figure 81, a large value (10 f) reservoir capacitor sits on dv dd and a separate 10 f capacitor sits on av dd also, local small-value (01 f) capaci- tors are located at each v dd pin of the chip as per standard design practice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each av dd pin with trace lengths as short as possible connect the ground terminal of each of these capacitors directly to the underlying ground plane finally, note that at all times, the analog and digital ground pins on the part must be referenced to the same system ground reference point
ADUC841/aduc842/aduc843 rev. 0 | page 74 of 88 power consumption the currents consumed by the various sections of the part are shown in table 40 the core values given represent the current drawn by dv dd , while the rest (adc, dac, voltage ref) are pulled by the av dd pin and can be disabled in software when not in use the other on-chip peripherals (such as the watchdog timer and the power supply monitor) consume negligible current, and are therefore lumped in with the core operating current here of course, the user must add any currents sourced by the parallel and serial i/o pins, and sourced by the dac, in order to determine the total current needed at the supply pins also, current drawn from the dv dd supply increases by approxi- mately 10 ma during flash/ee erase and program cycles table 40. typical i dd of core and peripherals v dd = 5 v v dd = 3 v core (normal mode) (2.2 na m cl ) (1.4 na m cl ) adc 1.7 ma 1.7 ma dac (each) 250 a 200 a voltage ref 200 a 150 a since operating dv dd current is primarily a function of clock speed, the expressions for core supply current in table 40 are given as functions of m cl , the core clock freuency. plug in a value for m cl in hertz to determine the current consumed by the core at that oscillator freuency. since the adc and dacs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. and again, do not forget to include current sourced by i/o pins, serial port pins, dac outputs, and so forth, plus the additional current drawn during flash/ee erase and program cycles. a software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. brief descriptions of idle and power-down modes follow. power saving modes in idle mode, the oscillator continues to run, but the core clock generated from the pll is halted the on-chip peripherals continue to receive the clock, and remain functional the cpu status is preserved with the stack pointer and program counter, and all other internal registers maintain their data during idle mode port pins and dac output pins retain their states in this mode the chip recovers from idle mode upon receiving any enabled interrupt, or upon receiving a hardware reset in full power-down mode, both the pll and the clock to the core are stopped the on-chip oscillator can be halted or can continue to oscillate, depending on the state of the oscillator power-down bit in the pllcon sfr the tic, being driven directly from the oscillator, can also be enabled during power- down all other on-chip peripherals are, however, shut down port pins retain their logic levels in this mode, but the dac output goes to a high impedance state (three-state) during full power-down mode, the part consumes a total of approximately 20 a there are five ways of terminating power-down mode: asserting the reset pin (pin 15) returns to normal mode. all registers are set to their default state and program execution starts at the reset vector once the reset pin is de-asserted. cycling power all registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. time interval counter (tic) interrupt power-down mode is terminated, and the cpu services the tic interrupt. the reti at the end of the tic isr returns the core to the instruction after the one that enabled power-down. i 2 c or spi interrupt power-down mode is terminated, and the cpu services the i 2 c/spi interrupt. the reti at the end of the isr returns the core to the instruction after the one that enabled power-down. note that the i 2 c/spi power-down interrupt enable bit (seripd) in the pcon sfr must be set to allow this mode of operation. int0 interrupt power-down mode is terminated, and the cpu services the int0 interrupt. the reti at the end of the isr returns the core to the instruction after the one that enabled power-down. the int0 pin must not be driven low during or within two machine cycles of the instruction that initiates power-down mode. note that the int0 power-down interrupt enable bit (int0pd) in the pcon sfr must be set to allow this mode of operation. power-on reset (por) an internal por is implemented on the ADUC841/aduc842/ aduc843 3 v part for dv dd below 2.45 v, the internal por holds the part in reset. as dv dd rises above 2.45 v, an internal timer times out for approximately 128 ms before the part is released from reset. the user must ensure that the power supply has reached a stable 2.7 v minimum level by this time. likewise on power-down, the internal por holds the part in reset until the power supply has dropped below 1 v. figure 82 illustrates the operation of the internal por in detail. 128ms tp 1.0v tp 128ms tp 2.45v tp 1.0v tp internal core reset dv dd 03260-0-082 figure 82. internal por operation
ADUC841/aduc842/aduc843 rev. 0 | page 75 of 88 5 v part for dv dd below 4.5 v, the internal por holds the part in reset. as dv dd rises above 4.5 v, an internal timer times out for approximately 128 ms before the part is released from reset. the user must ensure that the power supply has reached a stable 4.75 v minimum level by this time. likewise on power-down, the internal por holds the part in reset until the power supply has dropped below 1 v. figure 83 illustrates the operation of the internal por in detail. 128ms 1.0v 128ms 4.75v 1.0v tp internal core reset dv dd 03260-0-096 figure 83. internal por operation grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to grounding and pc board layout of ADUC841/ aduc842/aduc843 based design s to achieve optimum performance from the adc and the dacs although the parts have separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the part, as illustrated in the simplified example of figure 84a in systems where digital and analog ground planes are connected together somewhere else (for example, at the systems power supply), they cannot be connected again near the part since a ground loop would result in these cases, tie all the parts agnd and dgnd pins to the analog ground plane, as illustrated in figure 84b in systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa the part can then be placed between the digital and analog sections, as illustrated in figure 84c in all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground make sure the return paths for all currents are as close as possible to the paths that the currents took to reach their destinations for example, do not power components on the analog side of figure 84b with dv dd since that would force return currents from dv dd to flow through agnd also, try to avoid digital currents flowing under analog circuitry, which could happen if the user places a noisy digital chip on the left half of the board in figure 84c whenever possible, avoid large discontinuities in the ground plane(s) (like those formed by a long trace on the same layer), since they force return signals to travel a longer path and of course, make all connec- tions to the ground plane directly, with little or no trace separating the pin from its via to ground if the user plans to connect fast logic signals (rise/fall time ns) to any of the parts digital inputs, a series resistor should be added to each relevant line to keep rise and fall times longer than ns at the parts input pins a value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the part and from affecting the accuracy of adc conversions dgnd agnd place analog components here place digital components here gnd place analog components here place digital components here dgnd a agnd place analog components here place digital components here b c 03260-0-083 figure 84 system grounding schemes
ADUC841/aduc842/aduc843 rev. 0 | page 76 of 88 c1+ v+ c1? c2+ c2? v? t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm202 1 2 3 4 5 6 7 8 9 dv dd 9-pin d-sub female dv dd 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 dv dd 1k : dv dd 1k : 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 11.0592mhz (ADUC841) 32.768khz (aduc842/aduc843) dv dd av dd av dd agnd c ref v ref dac0 dac1 dv dd dgnd psen ea dgnd dv dd xtal2 xtal1 reset rxd txd dv dd dgnd not connected in this example ADUC841/aduc842/aduc843 adc0 adc7 analog input vref output dac outpu t 03260-0-084 figure 85. example system (pqfp package), dacs not present on aduc843 other hardware considerations to facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware to allow easy access to download, debug, and emulation modes. in-circuit serial download access nearly all ADUC841/aduc842/aduc843 designs want to take advantage of the in-circuit reprogrammability of the chip this is accomplished by a connection to the ADUC841/aduc842/ aduc843s uart, which reuires an external rs-232 chip for level translation if downloading code from a pc basic configura- tion of an rs-232 connection is illustrated in figure 8 with a simple adm202 based circuit if users would rather not design an rs-232 chip onto a board, refer to application note uc006, a 4-wire uart-to-pc interface , (at wwwanalogcom/microconverter) for a simple (and ero-cost-per-board) method of gaining in- circuit serial download access to the part in addition to the basic uart connections, users also need a way to trigger the chip into download mode this is accom- plished via a 1 k pull-down resistor that can be umpered onto the psen pin, as shown in figure 8 to get the part into download mode, simply connect this umper and power-cycle the device (or manually reset the device, if a manual reset button is available), and it will be ready to serially receive a new program with the umper removed, the device comes up in normal mode (and runs the program) whenever power is cycled or reset is toggled
ADUC841/aduc842/aduc843 rev. 0 | page 77 of 88 note that psen is normally an output (as described in the external memory interface section) and is sampled as an input only on the falling edge of reset, i.e., at power-up or upon an external manual reset. note also that if any external circuitry unintentionally pulls psen low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. to pre- vent this, ensure that no external signals are capable of pulling the psen pin low, except for the external psen jumper itself. embedded serial port debugger from a hardware perspective, entry into serial port debug mode is identical to the serial download entry seuence described in the preceding section in fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways note that the serial port debugger is fully contained on the part (unlike rom monitor type debuggers), and therefore no external memory is needed to enable in-system debug sessions single-pin emulation mode also built into the part is a dedicated controller for single-pin in-circuit emulation (ice) using standard production ADUC841/ aduc842/aduc843 devices in this mode, emulation access is gained by connection to a single pin, the ea pin normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier to enable single-pin emulation mode, however, users need to pull the ea pin high through a 1 k resistor, as shown in figure 8 the emulator then connects to the 2-pin header also shown in figure 8 to be compatible with the standard connector that comes with the single-pin emulator available from accutron limited (wwwaccutroncom), use a 2-pin 01 inch pitch friction lock header from molex (wwwmolexcom) such as their part number 22-2-2021 be sure to observe the polarity of this header as represented in figure 8, when the friction lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top) typical system configuration the typical configuration shown in figure 8 summaries some of the hardware considerations that were discussed in previous sections development tools there are two models of development tools available for the ADUC841/aduc842/aduc843: x quickstart tm entry-level development system x quickstart pluscomprehensive development system these systems are described briefly in the following sections quickstart development sstem the quickstart development system is an entry-level, low cost development tool suite supporting the parts the system consists of the following pc based (windows compatible) hardware and software development tools hardware evaluation board and serial port programming cable software serial download software miscellaneous cd-rom documentation and prototype device a brief description of some of the software tools and components in the quickstart development system follows downloadin-circuit serial downloader the serial downloader is a windows application that allows the user to serially download an assembled program (intel hexadeci- mal format file) to the on-chip program flash memory via the serial com1 port on a standard pc application note uc004 details this serial download protocol and is available from wwwanalogcom/microconverter aspireide the aspire integrated development environment is a windows application that allows the user to compile, edit, and debug code in the same environment the aspire software allows users to debug code execution on silicon using the microconverter uart serial port the debugger provides access to all on-chip peripherals during a typical debug session as well as single step, animate, and break-point code execution control note that the aspire ide is also included as part of the quickstart plus system as part of the quickstart plus system, the aspire ide also supports mixed level and c source debug this is not available in the quickstart system, but there is an example proect that demonstrates this capability quickstart plus development system the quickstart plus development system offers users enhanced nonintrusive debug and emulation tools the system consists of the following pc based (windows compatible) hardware and software development tools hardware prototype board accutron nonintrusive single-pin emulator software aspire integrated development environment features full c and assembly emulation using the accutron single pin emulator miscellaneous cd-rom documentation
ADUC841/aduc842/aduc843 rev. 0 | page 78 of 88 timing specifications 1, 2, 3 table 41. av dd =2.7 v to 3.6 v or 4.75 v to 5.25 v, dv dd = 2.7 v to 3.6 v or 4.75 v to 5.25 v; all specifications t min to t max , unless otherwise noted parameter 32.768 khz external crystal aduc842/aduc843 cloc input (external clock driven xtal1) min typ max unit t c xtal1 period 30.52 s t cl xtal1 width low 6.26 s t ch xtal1 width high 6.26 s t cr xtal1 rise time 9 ns t cf xtal1 fall time 9 ns 1/t core aduc842/aduc843 core clock freuency 4 0.131 16.78 mhz t core aduc842/aduc843 core clock period 5 0.476 s t cc aduc842/aduc843 machine cycle time 6 0.059 0.476 7.63 s 1 ac inputs during testing are driven at dv dd 0.5 v for a logic 1 and 0.45 v for logi c 0. timing measurements are made at v ih min for logic 1 and v il max for logic 0, as shown in figure 87. 2 for timing purposes, a port pin is no long er floating when a 100 mv change from load voltage occurs. a port pin begins to floa t when a 100 mv change from the loaded v oh /v ol level occurs, as shown in figure 87. 3 c load for all outputs = 80 pf, unless otherwise noted. 4 aduc842/aduc843 internal pll lock s onto a multiple (512 times) of the 32.768 khz external crysta l freuency to provide a stabl e 16.78 mhz internal clock for the system. the core can operate at this freuency or at a binary submultiple called coreclk, selected via the pllcon sfr. 5 this number is measured at the default coreclk operating freuency of 2.09 mhz. 6 aduc842/aduc843 machine cycle time is nominally define d as 1/corecl. parameter variable external crystal ADUC841 cloc input (external clock driven xtal1) min typ max unit t c xtal1 period 62.5 1000 ns t cl xtal1 width low 20 ns t ch xtal1 width high 20 ns t cr xtal1 rise time 20 ns t cf xtal1 fall time 20 ns 1/t core ADUC841 core clock freuency 0.131 20 mhz t core ADUC841 core clock period 0.476 s t cc ADUC841 machine cycle time 0.05 0.476 7.63 s t ch t cl t c t cf t cr 03260-0-085 figure 86. xtal1 input dv dd 0.5v 0.45v 0.2dv dd + 0.9v test points 0.2dv dd 0.1v v load 0.1v v load v load + 0.1v timing reference points v load 0.1v v load v load 0.1v 03260-0-086 figure 87. timing waveform characteristics
ADUC841/aduc842/aduc843 rev. 0 | page 79 of 88 parameter 16 mhz core clk 8 mhz core clock external data memor read ccle min max min max unit t rlrh rd pulse width 60 125 ns t avll address valid after ale low 60 120 ns t llax address hold after ale low 145 290 ns t rldv rd low to valid data in 48 100 ns t rhdx data and address hold after rd 0 0 ns t rhdz data float after rd 150 625 ns t lldv ale low to valid data in 170 350 ns t avdv address to valid data in 230 470 ns t llwl ale low to rd or wr low 130 255 ns t avwl address valid to rd or wr low 190 375 ns t rlaz rd low to address float 15 35 ns t whlh rd or wr high to ale high 60 120 ns 03260-0-087 ale (o) port 0 (i/o) port 2 (o) t whlh t lldv t llwl t rlrh t avwl t llax t avll t rlaz t rhdx t rhdz t avdv a0
ADUC841/aduc842/aduc843 rev. 0 | page 80 of 88 parameter 16 mhz core clk 8 mhz core clock external data memor write ccle min max min max unit t wlwh wr pulse width 65 130 ns t avll address valid after ale low 60 120 ns t llax address hold after ale low 65 135 ns t llwl ale low to rd or wr low 130 260 ns t avwl address valid to rd or wr low 190 375 ns t vwx data valid to wr transition 60 120 ns t vwh data setup before wr 120 250 ns t whx data and address hold after wr 380 755 ns t whlh rd or wr high to ale high 60 125 ns 03260-0-088 ale (o) port 2 (o) t whlh t wlwh t llwl t avwl t llax t avll t vwx t vwh t whx a0
ADUC841/aduc842/aduc843 rev. 0 | page 81 of 88 parameter i 2 c compatible interface timing min max unit t l sclock low pulse width 1.3 s t h sclock high pulse width 0.6 s t shd start condition hold time 0.6 s t dsu data setup time 100 s t dhd data hold time 0.9 s t rsu setup time for repeated start 0.6 s t psu stop condition setup time 0.6 s t buf bus free time between a stop condit ionand a start condition 1.3 s t r rise time of both sclock and sdata 300 ns t f fall time of both sclock and sdata 300 ns t sup 1 pulse width of spike suppressed 50 ns 1 input filtering on both the sclock and sdata inputs suppresses noise spikes less than 50 ns. msb t buf sdata (i/o) sclk (i) stop condition start condition repeated start lsb ack msb 1 2-7 8 9 1 s(r) ps t psu t dsu t shd t dhd t sup t dsu t dhd t h t sup t l t rsu t r t r t f t f 03260-0-091 figure 90. i 2 c compatible interface timing
ADUC841/aduc842/aduc843 rev. 0 | page 82 of 88 parameter spi master mode timing (cpha = 1) min typ max unit t sl sclock low pulse width 1 476 ns t sh sclock high pulse width 1 476 ns t dav data output valid after sclock edge 50 ns t dsu data input setup time befo re sclock edge 100 ns t dhd data input hold time af ter sclock edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns 1 characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 bits in pllcon sfr set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 mhz. b. spi bit-rate selection bits spr1 and spr0 in spicon sfr set to 0 and 0, respectively. sclock (cpol = 0) t dsu sclock (cpol = 1) mosi miso msb lsb lsb in bits 6?1 bits 6?1 t dhd t dr t dav t df t sh t sl t sr t sf msb in 03260-0-092 figure 91. spi master mode timing (cpha = 1)
ADUC841/aduc842/aduc843 rev. 0 | page 83 of 88 parameter spi master mode timing (cpha = 0) min typ max unit t sl scloc low pulse width 1 476 ns t sh scloc high pulse width 1 476 ns t dav data output valid after scloc edge 50 ns t dosu data output setup before scloc edge 150 ns t dsu data input setup time befo re scloc edge 100 ns t dhd data input hold time af ter scloc edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr scloc rise time 10 25 ns t sf scloc fall time 10 25 ns 1 characterized under the following conditions: a. core clock divider bits cd2, cd1, and cd0 bits in pllcon sfr set to 0, 1, and 1, respectively, i.e., core clock freuency = 2.09 mhz. b. spi bit-rate selection bits spr1 and spr0 in spicon sfr set to 0 and 0, respectively. scloc (cpol = 0) t dsu scloc (cpol = 1) mosi miso msb lsb lsb in bits 61 bits 61 t dhd t dr t dav t df t dosu t sh t sl t sr t sf msb in 03260-0-093 figure 92. spi master mode timing (cpha = 0)
ADUC841/aduc842/aduc843 rev. 0 | page 84 of 88 parameter spi slave mode timing (cpha = 1) min typ max unit t ss ss to scloc edge 0 ns t sl scloc low pulse width 330 ns t sh scloc high pulse width 330 ns t dav data output valid after scloc edge 50 ns t dsu data input setup time befo re scloc edge 100 ns t dhd data input hold time af ter scloc edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr scloc rise time 10 25 ns t sf scloc fall time 10 25 ns t sfs ss high after scloc edge 0 ns miso mosi scloc (cpol = 1) scloc (cpol = 0) ss msb bits 61 lsb bits 61 lsb in t dhd t dsu t dr t df t dav t sh t sl t sr t sf t sfs msb in t ss 03260-0-094 figure 93. spi slave mode timing (cpha = 1)
ADUC841/aduc842/aduc843 rev. 0 | page 85 of 88 parameter spi slave mode timing (cpha = 0) min typ max unit t ss ss to scloc edge 0 ns t sl scloc low pulse width 330 ns t sh scloc high pulse width 330 ns t dav data output valid after scloc edge 50 ns t dsu data input setup time befo re scloc edge 100 ns t dhd data input hold time af ter scloc edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr scloc rise time 10 25 ns t sf scloc fall time 10 25 ns t doss data output valid after ss edge 20 ns t sfs ss high after scloc edge ns miso mosi scloc (cpol = 1) scloc (cpol = 0) ss msb bits 61 lsb bits 61 lsb in t dhd t dsu t dr t df t dav t doss t sh t sl t sr t sf t sfs msb in t ss 03260-0-095 figure 94. spi slave mode timing (cpha = 0)
ADUC841/aduc842/aduc843 rev. 0 | page 86 of 88 outline dimensions seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 14.15 13.90 sq 13.65 7.80 ref 10.20 10.00 sq 9.80 0.38 0.22 view a rotated 90 ccw 7 0 2.10 2.00 1.95 0.13 min coplanarity compliant to jedec standards mo-112-ac-1 figure 95. 52-lead plastic quad flatpack [mqfp] (s-52) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 bottom view 6.25 6.10 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref
ADUC841/aduc842/aduc843 rev. 0 | page 87 of 88 ordering guides table 42. ADUC841 ordering guide model supply voltage v dd user program code space temperature range package description package option ADUC841bs62-5 5 62 40c to +85c 52- lead plastic uad flatpack s-52 ADUC841bs62-3 3 62 40c to +85c 52- lead plastic uad flatpack s-52 ADUC841bcp62-5 5 62 40c to +85c 56-lead chip scale package cp-56 ADUC841bcp62-3 3 62 40c to +85c 56-lead chip scale package cp-56 ADUC841bcp8-5 5 8 40c to +85c 56-lead chip scale package cp-56 ADUC841bcp8-3 3 8 40c to +85c 56-lead chip scale package cp-56 eval-ADUC841s 5 uickstart development system eval-ADUC841sp 2 5 uickstart plus development system table 43. aduc842 ordering guide model supply voltage v dd user program code space temperature range package description package option aduc842bs62-5 5 62 40c to +85c 52- lead plastic uad flatpack s-52 aduc842bs62-3 3 62 40c to +85c 52- lead plastic uad flatpack s-52 aduc842bcp62-5 5 62 40c to +85c 56-lead chip scale package cp-56 aduc842bcp62-3 3 62 40c to +85c 56-lead chip scale package cp-56 aduc842bcp32-5 5 32 40c to +85c 56-lead chip scale package cp-56 aduc842bcp32-3 3 32 40c to +85c 56-lead chip scale package cp-56 aduc842bcp8-5 5 8 40c to +85c 56-lead chip scale package cp-56 aduc842bcp8-3 3 8 40c to +85c 56-lead chip scale package cp-56 eval-aduc842s 5 uickstart development system eval-aduc842sp 2 5 uickstart plus development system table 44. aduc843 ordering guide model supply voltage v dd user program code space temperature range package description package option aduc843bs62-5 5 62 40c to +85c 52- lead plastic uad flatpack s-52 aduc843bs62-3 3 62 40c to +85c 52- lead plastic uad flatpack s-52 aduc843bcp62-5 5 62 40c to +85c 56-lead chip scale package cp-56 aduc843bcp62-3 3 62 40c to +85c 56-lead chip scale package cp-56 aduc843bcp32-5 5 32 40c to +85c 56-lead chip scale package cp-56 aduc843bcp32-3 3 32 40c to +85c 56-lead chip scale package cp-56 aduc843bcp8-5 5 8 40c to +85c 56-lead chip scale package cp-56 aduc843bcp8-3 3 8 40c to +85c 56-lead chip scale package cp-56 eval-aduc842s 1 5 uickstart development system eval-aduc842sp 1, 2 5 uickstart plus development system 1 the only difference between the aduc842 and aduc843 parts is the voltage output dacs on the aduc842; thus th e evaluation system for the aduc842 is also suitable for the aduc843. 2 the uickstart plus system can only be ordered directly from accutron. it can be purchased from the website www.accutron.com.
ADUC841/aduc842/aduc843 rev. 0 | page 88 of 88 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03260-0-11/03(0)

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